Minimizing noise in voltage controlled ring oscillator

[adithyasunil26]

Hi everyone

I am trying to minimize the phase noise in a voltage-controlled ring oscillator circuit. I have a simple circuit consisting of CMOS inverters stages and a variable capacitance at each stage controlled by a control signal. How should I go about minimizing the phase noise in this circuit?

 

[adithyasunil26]

I am trying to minimize the phase noise in a voltage-controlled ring oscillator circuit. I have a simple circuit consisting of CMOS inverters stages and a MOS varactor at each stage controlled by a control signal. How should I go about minimizing the phase noise in this circuit?
Any suggestions will be helpful.

 

[dick_freebird]

One key is to make each stage's transition as
fast as possible. This minimizes the conversion
of voltage noise to phase noise across the
transition-slope. But the problem is that you
are deliberately degrading that transition time,
to gain control of frequency. You could try
making each "inverter" a three-stage to get
more gain and faster edges at the cost of a
lower max frequency.

Feeding the RO with a good LDO that can knock
down external noise sources, should help.

Good close-in decoupling can help the RO not
"talk to itself" so much.

 

[danadakk]

I assume you saw this -

http://www-smirc.stanford.edu/papers/Orals98s-ali.pdf

http://www.cecs.uci.edu/~papers/compendium94-03/papers/2000/islped00/pdffiles/10_4.pdf

Also pay special attention to bypass Cap performance at high freq. Not all Caps, for same C and technology, exhibit
same capability for ESR, filtering. Read the datasheet. Put
Cap in a 50 ohm jig and examine its performance with a
VNA or time domain response to a step.



Regards, Dana.

 

[adithyasunil26]

One key is to make each stage's transition as
fast as possible. This minimizes the conversion
of voltage noise to phase noise across the
transition-slope. But the problem is that you
are deliberately degrading that transition time,
to gain control of frequency. You could try
making each "inverter" a three-stage to get
more gain and faster edges at the cost of a
lower max frequency.

Feeding the RO with a good LDO that can knock
down external noise sources, should help.

Good close-in decoupling can help the RO not
"talk to itself" so much.

Thank you for taking the time to answer my query.

I actually require the higher frequency so adding stages does not seem to be an option.

I am using ideal sources in my simulation as of now so there should be no issue of external noises but I will keep this in mind for later.

Please can you elaborate on this close-in decoupling? I am a beginner and I do not get what you mean.

 

[KlausST]

Modeator action: Threads merged.

Klus

 

[biff44]

should we assume this is a ring oscillator on a semiconductor chip? i.e. not discrete?

if i were experimenting to get better phase noise, i would first look at the capacitor. the capacitor adds some time delay, which can be used to "tune" the frequency. but some capacitors are not really linear capacitors. Since you are putting a large signal voltage on this cap, with all sorts of harmonics, its C vs voltage response becomes important. if the capacitor is in fact non-linear with voltage, all those harmonics can fold back into the baseband oscillating frequency, and appear as noise (half amplitude noise, half phase noise). but since it is a digital circuit, and there are possibly voltage limiters in the circuitry, any AM noise converts pretty readily to phase noise (or time jitter).

I WOULD make sure the power supply is clean. i would be tempted to run it off of a linear voltage regulator, rather than a switching regulator. and like said, you need multiple bypass caps...like a 10pf in parallel with a 100 pf, in parallel with 0.1 uf, in parallel with 10 uF. probably ceramic for all of them.

I would also make sure the load is impedance buffered. if the load impedance the ring oscillator sees is changing (even if only by a minute amount) that will cause phase noise too. i would put a bunch of buffer gates in series at the output of the oscillator.

 

[adithyasunil26]

should we assume this is a ring oscillator on a semiconductor chip? i.e. not discrete?

if i were experimenting to get better phase noise, i would first look at the capacitor. the capacitor adds some time delay, which can be used to "tune" the frequency. but some capacitors are not really linear capacitors. Since you are putting a large signal voltage on this cap, with all sorts of harmonics, its C vs voltage response becomes important. if the capacitor is in fact non-linear with voltage, all those harmonics can fold back into the baseband oscillating frequency, and appear as noise (half amplitude noise, half phase noise). but since it is a digital circuit, and there are possibly voltage limiters in the circuitry, any AM noise converts pretty readily to phase noise (or time jitter).

I WOULD make sure the power supply is clean. i would be tempted to run it off of a linear voltage regulator, rather than a switching regulator. and like said, you need multiple bypass caps...like a 10pf in parallel with a 100 pf, in parallel with 0.1 uf, in parallel with 10 uF. probably ceramic for all of them.

I would also make sure the load is impedance buffered. if the load impedance the ring oscillator sees is changing (even if only by a minute amount) that will cause phase noise too. i would put a bunch of buffer gates in series at the output of the oscillator.

Yes, the oscillator is to be used as a part of the synthesizer.

I am in fact using a MOS varactor that is non-linear.

Okay, I will add the bypass caps and buffers.

 

[biff44]

Yes, the oscillator is to be used as a part of the synthesizer.

I am in fact using a MOS varactor that is non-linear.

Okay, I will add the bypass caps and buffers.

bypass caps can, or course, be off chip. you will probably want a 100 pf, .1 uf, and 4.7 uf in parallel, as a start.