shitansh
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Hi all,
Can any body tell me, How to calculate or know that, on what max frequency designed IP will work on FPGA? Does max freq is dependent on FPGA switching matrix speed?
For digital design max freq can be calculated from clk-out + propogation delay of output logic, where clock to outof filp-flop (in case of ASIC) is given by manufacturure, what in case of FPGA?
Thanks,
Shitansh Vaghela
Can any body tell me, How to calculate or know that, on what max frequency designed IP will work on FPGA? Does max freq is dependent on FPGA switching matrix speed?
For digital design max freq can be calculated from clk-out + propogation delay of output logic, where clock to outof filp-flop (in case of ASIC) is given by manufacturure, what in case of FPGA?
Thanks,
Shitansh Vaghela