Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Job opportunity @ Santa Clara & Hsinchu

Status
Not open for further replies.

entropy

Member level 2
Joined
Nov 13, 2004
Messages
49
Helped
8
Reputation
16
Reaction score
0
Trophy points
1,286
Location
Worldwide
Activity points
632
You can drop message to me if u r interested. Thank u.

Analog/RF IC Design Engineer Hsinchu 2009166 1
Qualifications: MSEE, PhD preferred,
with 2 years of strong experience in analog/RF circuit design. Must have excellent circuit design skills
and lab testing skills. Must be comfortable with performing a wide variety of tasks and enjoy working in
a team environment. Experience with highly integrated mixed-signal circuits, radio system/architecture,
CAD enhancements, ESD protection techniques is a must. Responsibilities: Design analog, mixed-signal
and radio frequency circuits for highly integrated CMOS transceivers. These circuits may include
amplifiers, filters, voltage regulators, data converters (DACs/ADCs), phase-locked loops (PLL's), delayedlock
loops (DLL's), switched-capacitor circuits, power amplifiers, low noise amplifiers, mixers and high
speed serial data interfaces. Responsible for developing and supporting the analog/RF blocks
-----------------------------------------------------------------------------
Please send your resume or CV to noagain.at.hotmail.dot.com

DigitalDesign Engineer Santa Clara 2009284 1
Responsibilities: We are looking for an individual who is creative,
motivated, energetic, pleasant to work with, who puts the group
above self to complement our team. The candidate will be
responsible for RTL to GDSII implementation of digital designs and
test structures. The candidate will also participate in flow
development for advance process nodes in 65nm and beyond.
Qualifications: MS or above in EE/CS or related discipline 3+ years
of experience in relevant position. Must have taped out designs at
65nm or below. Must have experience planning and implementing
high cell count design blocks with multiple macros. Experience in
taping out top level physical implementation of hierarchial design,
and flat designs highly valued. The candidate must possess detailed
command of Cadence SOC Encounter and/or Synopsys Astro/IC
Compiler place and route tools. The ideal candidate will have a
solid understanding of all aspects of front to back design (including
synthesis, DFT, floor-planning, power-planning, placement, CTS,
routing, SI, IR/EM, timing closure, DFM, physical verification flows)
and be able to work independently with minimal guidance. Prior
experience in low power designs is strongly desired. Excellent
knowledge in TCL, PERL, Makefiles, C/C++, Skill code highly valued.
Ideal candidate should also possess intimate knowledge, and have
prior experience with implementing a DDR/DDR2/DDR3 interface.
-----------------------------------------------------------------------------
Please send your resume or CV to noagain.at.hotmail.dot.com

Design Engineer (DFT) Santa Clara 2009257 1 Responsibilities: The selected person
will initially be responsible for all test pattern generation for Mobile devices. The position will
then expand to other areas of core digital design. Qualifications: Education: B.S.E.E. (M.S.E.E) Preferred
Experience: 2-5 Years Industry Digital Design Experience Other: Experience in Design-For-Test (DFT)
useful Excellent communication skills Must be able to work in a fast paced environment.
-----------------------------------------------------------------------------
Please send your resume or CV to noagain.at.hotmail.dot.com
 

DFT position is closed. Thank you for your attention.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top