Is there a same mechanism JTAG in ARM for FPGA Xilinx

[stackprogramer]

Hi, I am developing some FPGA boards. For debugging I used testbench and simulations. But sometimes despite that simulation is ok, After synthesis, my blocks don't work....
I have challenges in debugging my FPGA... In Verilog code, I had some clocks and reg...
My question is: can I see reg value (in module Verilog) like ARM in real-time?
Is any same mechanism for FPGA Xilinx? I need a way to make me fast in debuging....

 

[dpaul]

@stackprogramer
My question is: can I see reg value (in module Verilog) like ARM in real-time?
I do not know what is that, I am not a firmware developer!

But yes you can see what's going on inside the FPGA by inserting a Xilinx ILA core and then setting the trigger mechanism.

But sometimes despite that simulation is ok, After synthesis, my blocks don't work....
But I have difficulty in understanding your English. In a technical "this" and "that" have less meaning, so please be specific. What is not working?
How do you know your design fails or does not behave as expected?
Have you constrained your design properly? Has synthesis passed?
Has Place and Route stage passed?
Could you generate a bitstream and run it on your target FPGA?

 

[ads-ee]

There is something called simulation synthesis mismatch, that usually occurs when you don't write properly synthesizable HDL code. There are a lot of features in both Verilog and VHDL that can't be synthesized and there are ways of coding that result in synthesis results to differ from the simulation. Without seeing all of your code nobody here can point out those types of issues.