is the verilog code correct???

[jameela]

is the following code correct as explained in comments???...its giving zero in both cases....what cud be the alternative?


input [3:0]r;
reg [3:0] e_xk;
reg e_xk1; //output declared as reg




e_xk={r/8}; // bits divided by 8

begin

if (e_xk<=4'd 2) // if e_xk is equal to or less than 0.5 , e_xk1 should be 0

e_xk1=0;

else

if (e_xk>4'd 2) //if e_xk is greater than 0.5 e_xk1 should be 1

e_xk1=1;

 

[mersault]

your input has 4 bits.
If you divide it by 8 you are shifting 3 times, so, the result is 000e_xk[3]
This last value could be 1 or 0, and then is always minor than 2.

This is the reason why you are getting always a 0.

with 4 bits the max dec value that you can obtain is 15, divided by 8 is always minor than 2. I think that you want a 16 dec value in your input. In that case, your input has to have 5 bits.

 

[jameela]

i made the input of 5 bits but it cud not help me...result is still all 0

 

[mrflibble]

Did you declare e_xk1 as an output earlier on in the module? Can't tell from your code...

So maybe make it:

input [3:0] r;
output reg e_xk1;

etc...


Or you could just do:

input [3:0] r;
output e_xk1; // note the lack of register
assign e_xk1 = r[3]; // since all you are doing is divide by 8 == shift by 3.

Did you intend the output e_xk1 to be a combinatorial? Or is the registered approach wanted but the clock is missing? Possibly **broken link removed** or **broken link removed** might clarify things. You might also want to google "verilog combinatorial vs sequential".

hope that helps.

 

[jameela]

yes e_xk1 is an output...sory not to mention


i tried ur approach using:

assign e_xk1 = r[3]; // since all you are doing is divide by 8 == shift by 3.


but it gives e_xk1=1 only when r=8.....when r is less than 8 e.g r=7 it gives 0

i want that when r is greater than 4 so e_xk1 should give 1 and 0 when vice versa

and one more thing i would like to mention that i used the if else code at another place without using begin end and it gave correct results....while here i cant avoid using begin end before and after the if else statements....but its leading to wrong ans

Added after 2 minutes:

and yes i intend the output e_xk1 to be a combinatorial one

 

[mrflibble]

Sorry about that.

"i want that when r is greater than 4 so e_xk1 should give 1 and 0 when vice versa"

assign e_xk1 = | (r[3:2]); // that's not divide by 8, that's divide by 4!

Note that I took the libery to translate your "r is greater than 4" from your previous comment to "r is equal to or greater than 4".

Hopefully this helps.