I'd like to export the digital signal to the zybo-z7 20 board PMOD output.

[Jihwan_Park]

Hi,
I'm totally beginner in FPGA board.
My board is Zybo Z7-20
I want to output four digital signals like a=0110, b=0010, c=0111, d=0001 with 200 us period.

Therefore I wrote the code like this :

module gate_signal(a, b, c, d);
output a;
output b;
output c;
output d;
always begin
a=0;b=0;c=0;d=0; #50000;
a=1;b=0;c=1;d=0; #50000;
a=1;b=1;c=1;d=0; #50000;
a=0;b=0;c=1;d=1; #50000;
end
endmodule

Moreover, My .xdc code like this :

##Pmod Header JA (XADC)
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { a }];
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { b }];
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { c }];
set_property -dict { PACKAGE_PIN K14 IOSTANDARD LVCMOS33 } [get_ports { d }];

However, there is an error like "[Synth 8-2576] procedural assignment to a non-register a is not permitted".
How can I fix my code?

Thank you.

 

[dpaul]

However, there is an error like "[Synth 8-2576] procedural assignment to a non-register a is not permitted".
How can I fix my code?

This is very likely because you have used blocking assignments inside an always block. An assign statement inside the always block is a call to procedural continuous assignment.

I believe you just want to simulate the code and view the waveforms.

Try out...
initial
begin
.
.
end

 

[ads-ee]

It has nothing to do with blocking assignments in the always block. The problem stems from the signal assignments being inside an always block, which means that must be declared as reg in the older Verilog standards (in SV you can use logic).

You would declare the ports with output reg a, etc.

FYI there is no point in synthesizing this as the code will result in the constants a=0, b=0, c=1, and d=1 being output on the pins. There will be no cycling through the values you specified. Besides that the #50000 is ignored by synthesis.

If you want to sequence through outputs you will need a clock, counters, and an FSM to determine when to send out the next value.

 

[Akanimo]

Verilog is not my thing but from the little I get, you need a clock that may just be an internally generated signal and you need to update a,b,c and d sequentially with that clock.