How to test the fpga base array?

[bjzhangwn]

Hello everyone, there IOB, SLICE, memory and other logic, as well as routing resources within the FPGA base array, whether the basic functions of the FPGA basearray can be traversed test? Is the interface and interconnect logic can traverse the test timing difference from the spec .

 

[ads-ee]

If I understand your question. The factory does this on a tester to speed bin sort the parts from the fab.

If your intention is to do this test yourself...good luck...IMO this is busy work (i.e. a huge waste of time) and adds no value to anything. It certainly won't have any level of coverage that would improve reliability.

 

[wtr]

During implementation place and route works out interconnectivity to meet timing.
You can constrain the tool to PAR items closer.
However if you want to generate a test for components used in
vivado you can do

launch_modelsim -mode [ behavioral | post_synthesis | post_implementation ] -type [ functional | timing ]

Where
-mode Specifies either a behavioral simulation of the HDL design sources to verify syntax and confirm
that the design performs as intended, a functional or timing simulation of the post-synthesis
netlist, or a functional or timing simulation of the post implementation design to verify circuit
operation after place and route. The default mode is behavioral.
-type [ functional | timing ] - (Optional) Cannot be used with -mode behavioral. Specifies
functional simulation of just the netlist, or timing simulation of the netlist and SDF file. The
default is functional. Post-synthesis timing simulation uses SDF component delays from the
synth_design command. Post-implementation timing simulation uses SDF delays from the
place_design and route_design commands.
Note Do not use -type with -mode behavioral, or the tool will return an error.