how to run program from n th clock pulse from begining???

[vasireddyrajesh3]

begin  -- process lfsr1
      
    if rst_n = '0' then                 -- asynchronous reset (active low)
      reg := (others => '1');
    elsif  RISING_EDGE(CLK) then  -- rising clock edge
     
		vreg := reg;
      for i in 1 to width loop
        fb := '0';
        for j in taps'range loop
          if fb=vreg(taps(j)-1) then
            fb := '0';
          else
            fb := '1';
          end if;
        end loop;  -- j
        for k in vreg'left downto 1  loop
          vreg(k) := vreg(k-1);
        end loop;  -- k
        vreg(0) := fb;
      end loop;  -- i
      reg := vreg;
      
  dout <= reg(0 to width-1);

this is the LFSR program . i want the out put(dout)(its 8bit) from 8 th clock pulse only... and from 8 th clock pulse it should run continuously for each clock . how to do that.

 

[TrickyDicky]

right - for a start - this looks like you're a software programmer. Do you understand that loops unroll for synthesis and produce chains of logic in your case?
You have also only posted a code snippet. What is taps? where are the declarations of vreg, reg and dout?

secondly, you're not very clear on what you want to do. Do you want the shift register to wait for 8 clock before it starts shifting?
thirdly, did you intend for dout to be unregistered?

---------- Post added at 10:21 ---------- Previous post was at 10:18 ----------

running the code through my head again, do you realise that the i loop is useless? the first loops 1 to width-1 do nothing, only the last loop does anything.

 

[vasireddyrajesh3]

Taps areoutputs of 1,2,3,7 Registers.vreg and Reg are variables.Dout is the output.this is lfsr program width and lengths are 8.now the program has to run for 7clocks .I don't want this out puts. From 8 clock I want output.how to modify this program.this program is working perfectly from 1st clock.but want output from
8 clock.

 

[TrickyDicky]

best thing for you to do - delete the code. Get out a pencil and a peice of paper. Draw the circuit you're trying to design. Then when you have that - start the VHDL again. Do not use variables, use signals, until you are confident you know what you're doing.
There are no designs that need variables.

 

[153rd]

When you're done with what Dicky said, use a loop, to count up a certain signal till 8, wich triggers an enable or something. shouldnt be too hard