How to reduce the offset voltage in differential amp.

[yikwon1]

I designed Bandgap reference using TSMC.

but, this bandgap reference voltage variation is larger than the expected.
it's about 70mV.

so, I guess that differential amplifier in BGR has larger offset voltage.

In this case, how can i reduce or remove the offset voltage.

Increasing the gain of differential amplifier and good layout considering
mismatch are all of things for that?

Are there any way to reduce the offset voltage?

-thanks.

 

[wpchan05]

I designed Bandgap reference using TSMC.

but, this bandgap reference voltage variation is larger than the expected.
it's about 70mV.

so, I guess that differential amplifier in BGR has larger offset voltage.

In this case, how can i reduce or remove the offset voltage.

Increasing the gain of differential amplifier and good layout considering
mismatch are all of things for that?

Are there any way to reduce the offset voltage?

-thanks.

what if you replace the differential amp by an ideal amp? would the variation be smaller?

 

[mandar_mahajan]

I guess u r getting offset on higher side.
It would be able to tell u something only after seeing ur schematic of op-amp.

 

[yikwon1]

Thanks for replies

Actually this results(BGR output voltage=1.175V~1.25V) are
measured results, not simulation.

So, I just think that this causes of it are offset voltage or BJT mismatching.

therefore, I want to know the reducing way for offset voltage.

Are there any other reasons for BGR's variations?

As you know, it's very hard to find the basic cause,
because I can't measure any point except the BGR output.

Thanks.

 

[suria3]

Hi,

If your measured results shows the offset error, first I believe it could be due to the opamp itself. As you stated above, the poor device mathing of the opamp layout itself could have triggered this. You have can re-simulate your pre-silicon simulation by intentionally introduces some device input mismatch to see this effect. Other factor diode mismatch as well.

 

[fencl]

Hi ,if there's any type of resistor you have used for BGR,take care of it for big process variation.

 

[yikwon1]

Thanks for replies.

I designed and simulated BGR block considering process variation
and LPE(parastic extraction).

The results of the simulation met the specification I expected
under FF,TT,SS,SF,FS and -40'C~80'C conditions.

To tell the true, I don't understand
why could not check it using simulation process.

Do I have to do something for detecting it in simulation process?

Thanks.

 

[tzg6sa]

Have you run Monte Carlo analysis for mismatch? The process corners do not count with the mismatch of the devices. The input transistors of the amp can be critical.
What are the sizes of the input transistors?