How to recovery the clock from T1/E1 transmission stream in FPGA?

[ch_wen]

Hi,

Is there anybody like to share your experience that how to recovery the clock from T1/E1 transmission stream in FPGA?

Thanks.

 

[omid_azmoon]

e1 t1 fpga

DSTI & DSTO & FOB & C4b & E2o : depence of what you want , all of it can be input or output ,and can use it in FPGA .If you have exact question mail me .

 

[Vonn]

e1 liu in fpga

1st you will need the framing pulse of your E1
2nd you must know the running bus (ST or GCI)
Then using an 2.048 MHz (for E1) and internal FPGA DLL you can recover the E1 clock to be in-phase with the framing pulse

 

[Black Jack]

e1 cdr

Hi,

Is there anybody like to share your experience that how to recovery the clock from T1/E1 transmission stream in FPGA?

Thanks.

If you want recover only clock you can use internal PLL, DLL in FPGA
(but see for lock range).

If you want also recover data structure you must have a recovered clock
(2.048 for E1 and 1.544 MHz for T1), and analyze stream for framing and superframing sync.

 

[jetset]

cdr e1

You may usa a resonant circuit to check synchronization of incoming signal, with local clock. Usually the clock is not recovered, just check synchronization.

 

[Black Jack]

e1 fpga design

You may usa a resonant circuit to check synchronization of incoming signal, with local clock. Usually the clock is not recovered, just check synchronization.

I`m agree with you.

Use both lout+ and lout- signals from LIU (but many LIU`s have resonant circuit
with external LC, e.g. EXAR XR-T56L85), OR`ed lout+ with NOT(lout-) - this give more transition for resonant circuit.

Use local PLL ( like VCXO-based) to more clear extracted clock from E1/T1 and for accurate sync. you design

 

[dinesh.4126]

Re: T1/E1 CDR in FPGA

Hi,
I am messed up with is that Suppsose E1 signal is coming from Transmitter which act as input to FPGA and we are doing Deframing of E1 implementaiom in FPGA.Now when E1 signal comes why cant directly we give to FPGA.
2)In CDR bascially its menas we need to synch. the incoming Data with 2.04MHZ clock which is internally generated from on Board Crystal.

Please reply so that I can figure out somehow.

Regards,