li_polaris
Newbie level 2
Hi!
I am a newbie in the timing analysis,in the process of learning timing analysis I find the output delay was so elusive,I think the Output Minimum Delay and Output maximum Delay should be "Output Minimum Delay = Th - <max data delay> + <min clock delay>
Output maximum Delay=T(period)+<max clock delay>-<min data delay>-Tsu",but the truth is not so.Some data shows that "output delay max= (Tdata_PCB(max) + TCL) - (Tclk2(min) - Tclk1ext(max) ) + Tsu output delay min= (Tdata_PCB(min) + TCL) - (Tclk2(max) – Tclk1ext(min) ) - Th".it's indigestible!
Is there anyone can help me?
thank you very much!
I am a newbie in the timing analysis,in the process of learning timing analysis I find the output delay was so elusive,I think the Output Minimum Delay and Output maximum Delay should be "Output Minimum Delay = Th - <max data delay> + <min clock delay>
Output maximum Delay=T(period)+<max clock delay>-<min data delay>-Tsu",but the truth is not so.Some data shows that "output delay max= (Tdata_PCB(max) + TCL) - (Tclk2(min) - Tclk1ext(max) ) + Tsu output delay min= (Tdata_PCB(min) + TCL) - (Tclk2(max) – Tclk1ext(min) ) - Th".it's indigestible!
Is there anyone can help me?
thank you very much!