How to calculate that max transition value for design?

[Nantha]

Hi all,

How synthesis people will desire the max transition value for design?? How to calculate that max transition for design??

[please note: I'm not asking about max transition violation.. I meant to set the max transition value before optimization]

Thanks in advance,

Regards,
Nantha

 

[phoenixpavan]

Re: About max transition

Hi Nantha,

The transition time of a net is the time required for its driving pin to change logic values. This transition time is based on the technology library data. For the nonlinear delay model (NLDM), output transition time is a function of input transition and output load. During optimization, Design Compiler attempts to make the transition time of each net less than the value of the max_transition attribute.

To change the maximum transition time restriction specified in a technology library, use the set_max_transition command. This command sets a maximum transition time for the nets attached to the identified ports or to all the nets in a design by setting the max_transition attribute on the named objects.

Design Compiler adds buffering to correct the max_transition violations. A common mistake is the assumption that the default_max_transition or the default_max_fanout constraint in the technology library applies to input ports. These constraints apply only to the output pins of cells within the library.Extremely conservative numbers for max_transition, max_fanout, or max_capacitance force Design Compiler to buffer nets excessively.

cheers

 

[SSTA]

Guys,

One question. If you do some new design, how to decide max_transition constraint for synthesis and place&route/STA? Is this something based on experince or there is a right way to decide the maximum allowed value for transition time?

Thanks in advance.

 

[yx.yang]

Guys,

One question. If you do some new design, how to decide max_transition constraint for synthesis and place&route/STA? Is this something based on experince or there is a right way to decide the maximum allowed value for transition time?

Thanks in advance.

Hi:
As "phoenixpavan" as said, there is a "max_transition" constraint for each input of the cell library gates. And DC will try to optimize to obey this constraint in your cell library.
So you just need set the transiton of the inputs of your "chip".
PS: There is just one points I don't agree with phoenixpavan: "A common mistake is the assumption that the default_max_transition or the default_max_fanout constraint in the technology library applies to input ports." I think "default_max_transition" constraint does apply to cell input pins.
Thanks.

 

[r53637]

Hi:
As "phoenixpavan" as said, there is a "max_transition" constraint for each input of the cell library gates. And DC will try to optimize to obey this constraint in your cell library.
So you just need set the transiton of the inputs of your "chip".
PS: There is just one points I don't agree with phoenixpavan: "A common mistake is the assumption that the default_max_transition or the default_max_fanout constraint in the technology library applies to input ports." I think "default_max_transition" constraint does apply to cell input pins.
Thanks.

I know what "Nantha" said: before we do a synthesis, how do we decide a max_transition_time for particular design?
For example: if the max_transition defined in standard cell is 3.2, and the maximum frequency of design is 48MHz, what will you set on max_transition_time in synthesis for all the clock buffers? We usually set it to 0.3ns but sometimes it causes large buffer to be inserted. We want to increase the number but we don't know what number is proper.

 

[kbulusu]

its all part of library characterization..if your .lib is poor or doesnt have gates which suffices your design needs, then you need to go back and select a diff lib or add few more gates which have faster transition time...synthesis tools honour what comes from .lib or if user has some some transition values, then it considers whatever value is pessimistic among user defined and .lib values ...