how much should i set the width of a finger in proper layout

[henrywent]

finger width in cmos

how much should i set the width of a finger in proper layout design? The process is 0.18um cmos, W/L=24u/0.2u, should i split it into 3 fingers with 8u/0.2, or 6 fingers with 4u/0.2, which scheme is better in terms of parasitic capacitance reduction and good matching? In general, how much should we set the width of the finger?
thanks!!

 

[erikl]

width of a finger

how much should i set the width of a finger in proper layout design? The process is 0.18um cmos, W/L=24u/0.2u, should i split it into 3 fingers with 8u/0.2, or 6 fingers with 4u/0.2, which scheme is better in terms of parasitic capacitance reduction and good matching? In general, how much should we set the width of the finger?
thanks!!

More fingers, more parasitic capacitance, but less parasitic resistance.

Here, from Behzad Razavi's book "Design of Analog CMOS Integrated Circuits", chapter 18.2.1 Multifinger Transistors the 2 most important rules:

1. on parasitic resistance: "As a rule of thumb, the width of each finger is chosen such that the resistance of the finger is less than the inverse transconductance associated with the finger. In low-noise applications, the gate resistance must be one-fifth to one-tenth of 1/gm." This sets the minimum number of fingers.

2. on parasitic capacitance: "..., the number of fingers multiplied by E (the distance between 2 adjacent poly-gate edges, i.e. the "length" of the active S/D region in between) must be much less than (total) W so as to minimize the S/D perimeter capacitance contribution." This sets the upper limit.

Good matching has not a lot to do with the actual number of fingers, but much more depends on good layout topology symmetry. This is an extra topic covered in chapter 18.2.2 Symmetry of the same book, extending over 5 pages (637 .. 642).

HTH! erikl

 

[henrywent]

cmos 0.18 multi finger razavi

thanks , i will check it out in the book

 

[jogladik]

parasitic capacitance reduction in layout

The choice of ratio in the construction of high-frequency transistors (meander, etc.)Progress In Electromagnetics Research Symposium 2007, Prague, Czech Republic, August 27-30
A Study of Layout Strategies in RF CMOS Design
John Richard E. Hizon, Marc D. Rosales, Honee Lynn B. Tan
Maria Cecilia N. Gutierrez, Louis P. Alarcon, and Del¯n Jay Sabido IX
Microelectronics and Microprocessors Laboratory
Department of Electrical and Electronics Engineering
University of the Philippines, Diliman, Quezon City, Philippines
tech up to 12.5 * 0.18
well on the characteristics of 10 * 0.18

 

[hafiz24]

how much is 2 fingers with

Many issues addressed already.

erikl was right to say about parasitic resistance and capacitance separately. But if you're considering effective RC, I think increasing fingers help [ IC Mask Design by Christopher Saint/Judy Saint, page: 93], so long as you're not space constraint. So I think, 6 fingers with 4u/0.2 is better.