How can metastability last more than one clock cycle?

[sps0987]

I kept seen papers saying metastability can last indefinitely theoretically, but how is it possible? If D transitions on the sampling clock edge, then Q goes meta stable, I can understand that. But if D lasts two clock cycles, regardless of what Q was in the first clock cycle(either metastable or settled), Q always transitions to D on clock cycle 2 after tpd doesn't it? Because D on clock cycle 2 meets tsu and th?

 

[danadakk]

An excellent discussion here -

https://www.ti.com/lit/an/sdya006/sdya006.pdf?ts=1610017801997&ref_url=https%253A%252F%252Fwww.google.com%252F

Infers because logic levels are no longer guaranteed.


Regards, Dana.

 

[dick_freebird]

Metastability comes from the relation between
clock and data time-of-arrival.

If the subsequent clock has the same data
transition timing associated with it then it
will have the same probability of entering
(or not leaving) metastable condition.

But a subsequent clock with setup / hold
times respected, will go to its proper state
(provided that this is a "normally constructed"
flip-flop, and not something oddball like a
dynamic DFF or a toggle-conected DFF
which depends on having a valid
predecessor state, to get a valid successor).

There's also the distinction between "invalid"
(not meeting VIH/VIL) and "unknown" (which
is the simulator's declaration; a physical
logic gate would decide one way or another
but once "X" is injected to the logic bed, it
may take one, multiple or infinite cycles to
scrub out depending on topology and site).

 

[ThisIsNotSam]

There's also the distinction between "invalid"
(not meeting VIH/VIL) and "unknown" (which
is the simulator's declaration; a physical
logic gate would decide one way or another
but once "X" is injected to the logic bed, it
may take one, multiple or infinite cycles to
scrub out depending on topology and site).

This.

I have seen students struggle with this concept for more than a decade now