help in which data to get from summary after simulation

[qwerty_asdf]

I have some questions. i am using xilinx and my device is a virtex6.


I managed to make my vhdl pass the post route simulation and gives me the right result. No i want to test it for different inputs, and check the results. My question is what measurements should i take?


I mean what i look so far is the total time, and the best case achievable clock from timing summary.


Are there any other that I should look so as to compare them? It is part of a project and I do not know what datas I must present, so to give a better look of my design and its perfomance.

 

[qwerty_asdf]

noone? I mean what do you look at when you run your code? only if it is working, time, something else?

 

[gongdori]

I usually look at the resource utilization and make sure that the resources used are within expected range.
Usually FPGA power supplies are designed for the worst case, but if you are designing for low power, it would be good to know how much power it would consume.