yag
Newbie level 1
Hi all;
I am trying to design a FD folded cascode (pmos input stage) op amp in cadence. When I look at in open loop, it's phase is ok, and the node voltages stay at their dc values. However when I make it closed loop via capacitive negative feedback the ac simulation gives the ac gain as expected however the phase is starting from 0 and then increasing with increasing slope. Also when I look at the nodes via transient analysis, it is seen that even without an input ac signal after a time the nodes got stuck at either vdd or vss.
I have tried the simulations both with CMFB and without but the result is the same. What can be the usual suspects?
I am trying to design a FD folded cascode (pmos input stage) op amp in cadence. When I look at in open loop, it's phase is ok, and the node voltages stay at their dc values. However when I make it closed loop via capacitive negative feedback the ac simulation gives the ac gain as expected however the phase is starting from 0 and then increasing with increasing slope. Also when I look at the nodes via transient analysis, it is seen that even without an input ac signal after a time the nodes got stuck at either vdd or vss.
I have tried the simulations both with CMFB and without but the result is the same. What can be the usual suspects?