Frequency behavior Class AB OTA

[mirror_pole]

Hey guys i have a "stupid" question,

Im analysing the following class AB OTA https://www.semanticscholar.org/pap...dc5e9204b0b80f8d1d6349db65b44964a868/figure/0

I checked all papers and a phd thesis concerning this topology, but everytime the gain calculations are only made for DC. Just asking myself why there is no frequency behavior calculation. Is it maybe to "obvious" for people who design circuits already for a long time to determine where the poles and zeros are?

 

[BradtheRad]

The article has diagrams including several graphs. The X axis was hidden until I zoomed out and saw it's in Hz from 1k to 1G.
Graphs include comon-mode gain and differential gain. Are these what you're looking for?

 

[mirror_pole]

hey, yeah exactly. This is the circuit with all the simulation results. Calculations for differential gain are only made for dc. Papers are based on a phd thesis, and even there the caculations are only made for dc.

Some other topologies i came across are analysed the same way and i just wonder why there is no frequency behavior analysis. I mean how is it possible to design such a circuit if you dont calculate poles and zeros?

 

[Dominik Przyborowski]

It is symmetrical current mirror OTA with only output nodes being high impedant.
There is no need for detailed frequency analysis. Dominant pole at output, GBW set by input transconductance and output cap, non dominant poles should be at least 3UGF what is achievable if transistors ft is ca N+4 times higher than UGF (N is current mirror ratio). The UGF is ca 100MHz so, for all available processes it is easily done.

 

[mirror_pole]

It is symmetrical current mirror OTA with only output nodes being high impedant.
There is no need for detailed frequency analysis. Dominant pole at output, GBW set by input transconductance and output cap, non dominant poles should be at least 3UGF what is achievable if transistors ft is ca N+4 times higher than UGF (N is current mirror ratio). The UGF is ca 100MHz so, for all available processes it is easily done.

Thank you! Concerning non dominant poles should be at least at 3UGF (unity gain frequency?): why exactly 3x and how is this related to ft of transistors should be ca N+4 times higher? Sorry if this are stupid questions, im just struggling with it.

 

[Dominik Przyborowski]

Concerning non dominant poles should be at least at 3UGF (unity gain frequency?)

For two pole system, if non dominant pole is placed at 3UGF than phase margin is ca to 71.6 degree (with 2UGF it is ca 59 degree, while for UGF it is 45 degree).

how is this related to ft of transistors should be ca N+4 times higher?

Ft is ca gm/cgs and represents intrinsic pole of transistor. In current mirror with ratio N, gate node has N+1 gate caps and "single" gm connected. So, the pole is set to gm/(N+1)/cgs=ft/(N+1). So, to ensure this pole is located at least at 3UGF, ft should be N+4 times higher than UGF.

The peak ft of nfet with L=100nm is ca 100GHz so 100MHz UGF set enough margin for most of the processes.

 

[mirror_pole]

Thank you very much!

--- Updated Jan 31, 2021 ---

For two pole system, if non dominant pole is placed at 3UGF than phase margin is ca to 71.6 degree (with 2UGF it is ca 59 degree, while for UGF it is 45 degree).


Ft is ca gm/cgs and represents intrinsic pole of transistor. In current mirror with ratio N, gate node has N+1 gate caps and "single" gm connected. So, the pole is set to gm/(N+1)/cgs=ft/(N+1). So, to ensure this pole is located at least at 3UGF, ft should be N+4 times higher than UGF.

The peak ft of nfet with L=100nm is ca 100GHz so 100MHz UGF set enough margin for most of the processes.

Concerning the current mirror OTA, from that paper: can i assume that the non dominant pole is at the pMOS of the top current mirror? (because in reality it is larger then the nmos, therefore cgs would be greater). Looking at the table they have 200MHz unity gain bandwidth. L=120nm for the transistor where i assume pnd (from the phd thesis), so ft would be around 80 GHz? So if i chose N=9 for example pnd=ft/10=9 Ghz therefore 9Ghz/200Mhz= 45? They have PM around 57 but from my calculation if should be huge. I dont see my stupid mistake

 

[Dominik Przyborowski]

sorry, I was not precise enough. Transit frequency creates pole for a single device. If we consider two devices in signal chain, then we can see pole at ft but 2nd order. So, at gates of M5 and M6 we have one pole at ft/(N+1), source of M4 shows another pole at ft as well as at source of M2.
The best way to find all poles/zeros is to calculate small signal transfer function. Sometimes, you can find "rules of thumb" to ensure ft>10 - 20UGF depending to number of stages in amplifier (what is related to number of transistors/nodes in circuit).


And about ft - for 120nm lenght it has a peak value around 100GHz - depending to operation region it can be lower as ft has linear - to square root dependency of current density.

 

[mirror_pole]

sorry, I was not precise enough. Transit frequency creates pole for a single device. If we consider two devices in signal chain, then we can see pole at ft but 2nd order. So, at gates of M5 and M6 we have one pole at ft/(N+1), source of M4 shows another pole at ft as well as at source of M2.
The best way to find all poles/zeros is to calculate small signal transfer function. Sometimes, you can find "rules of thumb" to ensure ft>10 - 20UGF depending to number of stages in amplifier (what is related to number of transistors/nodes in circuit).


And about ft - for 120nm lenght it has a peak value around 100GHz - depending to operation region it can be lower as ft has linear - to square root dependency of current density.

Thanks Dominik!
Actually i calculated the transfer functions for the seperate signal paths. For the top path i get 4 poles and 2 zero. Under certain conditions that the pole associated with the drain of M2 is made much higher then at source of M2 one pole cancels with a Zero. The other Zero appears at the double of the pole associated with the drain of M2. Therefore its a pole zero doublet i guess. The 2 other poles are associated with the drain of M4 and with the Source of M4 as u said.

For the bottom path i got 1 zero and 2 pols. The Pol associated with drain of M2 appears in both paths. Also the pol at the source of M2 is present and cancels with the zero the same way as for top path under the conditions as mentioned before, so only 1 pol is left.

When i calculate the total transfer function out of the 2 seperate ones i get an additional zero.

Now i kind of understand what u mean that there is actuall no need to make a frequency analysis . I mean the transfer function doesnt give much more insight. U can already tell from inspection that pnd has to be on the pmos current mirror. Interestingly the Pol associated with drain of M2 is close to pnd because from calculation u get 2*(N+1)Cgs instead of (N+1)Cgs which u get for top, but the top is a factor of 3 bigger because its p type. So these 2 poles affect PM the most i guess?

By the way what is the benefit to make the input stage n type instead of p type? I mean if i would make the input stage p type instead of n type the doublet will appear first and then the second (non dominant) pol. So i could cancel the second pol with the zero of the doublet?