FATAL_ERROR:Xst:Portability/export/Port_Main.h:143:1.17

[arunbv123]

module find(clk,reset,V,a,p,
);
parameter X=1;
parameter NUM=5;
parameter a1=2;//constants
parameter a2=2;
parameter b1=1;
parameter b2=1;

input clk,reset;
inout [0:NUM-1]V;
input [0:NUM-1]a;
input [0:NUM-1]p;



reg [0:NUM-1]ve;//temporary value
reg ab1,ab2;

assign V=vel;/*including this statement will introduce the error : FATAL_ERROR:Xstortability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at **broken link removed**


initial
begin
ab1=a1*b1;
ab2=a2*b2;
end

always @ (posedge clk or negedge reset)
begin
if (reset == 1'b0)
begin
end
else
begin
ve[0]<= x*ve[0] + ab1*(p[0]-a[0]);
ve[1]<= x*ve[1] + ab1*(p[1]-a[1]);
ve[2]<= x*ve[2] + ab1*(p[2]-a[2]);
ve[3]<= x*ve[3] + ab1*(p[3]-a[3]);
ve[4]<= x*ve[4] + ab1*(p[4]-a[4]);
end

end
endmodule

I given code above. ' V ' variable it is a inout port because the previous value is given as input and the new value is calculated and then stored in the same variable. As the inout port should be a wire. the calculation is done in behavioral block with a temporary register ' ve '. but including the assign statement to update V introduces the error mentioned.

FATAL_ERROR:Xstortability/export/Port_Main.h:143:1.17 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at Xilinx: Product Support & Documentation.