Explanation of Physical Design flow

[kumar_eee]

Hi All,
Can anyone explain me the Physical Design flow in detail?.

Kumar

 

[MarcS]

Re: Physical Design Flow

In detail? That would take a good-sized textbook to do. I brief, these are the major steps for the typical bottom-up digital IC physical design flow:
The physical design flow starts after synthesis is done.
The first step is to create a floorplan. This places all the big macro blocks (RAM, PLL, Analog blocks, etc) and assigns logical modules to be placed in particular regions of the chip.
The second step is placement and placement-based logical optimization. Usually called 'physopt'
The third step is clock tree synthesis (CTS)
The fourth step is post-CTS optimization. This is another pass of physopt to fix any timing issues caused by inserting the clock tree logic.
The fifth step is global routing
The sixth step is detailed routing. Typically clock nest are routed first and then other nets.
The seventh step is post-route optimization to clean up any remaining timing violations.
The eighth step is called "chip finishing" where a bunch of physical optimizations are added. Primarily via-doubling, metal-fill insertion, antenna fixing, critical area optimization through wire spreading, etc.
The ninth step is 'golden' or sign-off extration
The tenth step is sign-off timing verification
The eleventh step is layout-vs-schematic (LVS) and physical design-rule checking (DRC) signoff verification.
And that brings you to "tape-out", which is where the design goes into the manufacturing arena.
There are still a lot of steps after this (OPC, RET, Fracturing, etc), but they are not typically considered to be part of physical design.