Dual clock edge Synopsys Design Constraints (SDC) files

[coshy]

Hi.

Now, I'm trying to implement the DUT which has dual clock edge.

  always @(posedge clk or negedge clk or posedge reset_n) begin
    if(reset_n) begin
      num_counter <= 1'b0;
    end else begin
      num_counter <= num_counter  + 1;
    end
  end

But I don't know what am I supposed to make a SDC file if I want to use dual clock?
clk = 200Mhz, 50% duty.
There is no input delay and output delay and jitter suffs.

Can I just use like this?
create_clock -period 5 clk


one more thing,
If I use dual clock, then should I have to use posedge reset_n ? or can I use negedge reset_n?

  always @(posedge clk or negedge clk or negedge reset_n) begin
    if(!negedge ) begin
      num_counter <= 1'b0;
    end else begin
      num_counter <= num_counter  + 1;
    end
  end

 

[dpaul]

Can I just use like this?
create_clock -period 5 clk

Yes.
Now when you are using the falling edge, just use the switch -clock_fall (or whatever is equivalent in Syn SDC). For rising edge you need not mention anything (i.e. by default rising edge).

If I use dual clock, then should I have to use posedge reset_n ? or can I use negedge reset_n?

Use only one type of reset, remember it and stick to it through the complete design.

 

[coshy]

Yes.
Now when you are using the falling edge, just use the switch -clock_fall (or whatever is equivalent in Syn SDC). For rising edge you need not mention anything (i.e. by default rising edge).


Use only one type of reset, remember it and stick to it through the complete design.

Thanks dPaul,

Did you mean if I use "-clock_fall" in the commands, then does it mean I want to use dual clock?

create_clock -period 5-waveform {0 5} -name clk[get_ports clk] -clock_fall ?

 

[dpaul]

Did you mean if I use "-clock_fall" in the commands, then does it mean I want to use dual clock?

It meas that you are trying to put a constraint on the falling edge of the clock.

For creating clocks, the " create_clock -period 5 clk " will suffice. So no need to use...

create_clock -period 5-waveform {0 5} -name clk[get_ports clk] -clock_fall ?

But if you want to put any type of constraint on the clock edges, then comes the difference. By default for rising edge constraints you do not put any special switch.
But when you are specifying constraint for the falling edge then you need to specify the switch WHICH WOULD BE SIMILAR to " -clock_fall " (plz chk with Synopsys SDC documentation user guide as the what the switch actually is ).

And please read at least one the Synopsys SDC documentation user guide, it will be more than useful!