Gnemuri
Newbie
Hello Everyone, 
I'm studying the 5 Stages Pipelined version of Mips, but I got lost in this double data hazard example.
I'm pasting you what the book says about this:
"One complication is potential data hazards between the result of the instruction in the WB stage, the result of the instruction in the MEM stage, and the source operand of the instruction in the ALU stage. For example, when summing a vector of numbers in a single register, a sequence of instructions will all read and write to the same register:
add $1,$1,$2
add $1,$1,$3
add $1,$1,$4
In this case, the result is forwarded from the MEM stage
because the result in the MEM stage is the more recent result."
But why am i forwarding from the MEM Stage? If i try to execute the three instructions, I've got a data hazard at Clock Cicle 4 when the Instrucion 2 is in the EX stage, and in the Clock Cicle 5 when the Instruction 3 is from in its EX Stage.
So in my mind the solution is to:
Forward from the I1 to I2 at CC4 (Clock Cicle 4)
Forward from the I2 to I3 at CC5
But this would happen from EX/MEM stage in both cases, differently from the solution of the book.
Can anybody help me please?
Thank you in advance!
I'm studying the 5 Stages Pipelined version of Mips, but I got lost in this double data hazard example.
I'm pasting you what the book says about this:
"One complication is potential data hazards between the result of the instruction in the WB stage, the result of the instruction in the MEM stage, and the source operand of the instruction in the ALU stage. For example, when summing a vector of numbers in a single register, a sequence of instructions will all read and write to the same register:
add $1,$1,$2
add $1,$1,$3
add $1,$1,$4
In this case, the result is forwarded from the MEM stage
because the result in the MEM stage is the more recent result."
But why am i forwarding from the MEM Stage? If i try to execute the three instructions, I've got a data hazard at Clock Cicle 4 when the Instrucion 2 is in the EX stage, and in the Clock Cicle 5 when the Instruction 3 is from in its EX Stage.
So in my mind the solution is to:
Forward from the I1 to I2 at CC4 (Clock Cicle 4)
Forward from the I2 to I3 at CC5
But this would happen from EX/MEM stage in both cases, differently from the solution of the book.
Can anybody help me please?
Thank you in advance!