Design conversion to synthesizable verilog/vhdl

[np108]

I need to convert existing design (2 Pages with primitive logics) to synthesizable verilog/vhdl. My expectation is it should not take more than few hours for a working professional in the field. I also need a quick rundown of workflow pointers and industry practice on converting the source to xilinx cplds or other silicone (if recommended).

thank you