Demultiplexer

[Mancoba]

Hello everyone, I'm new here and currently working on a digital circuit design. I'm having trouble figuring out a concept for assembling 8x 1 to 8 demultiplexers in a way that consumes minimal digital outputs. I have an NI-DAQ card with 16 digital IO, and I want to use as few digital outputs from my DAQ card as possible—ideally just around 8 bits to control the demultiplexers. How can I solve this problem? Has anyone built something similar and has a sample circuit ready for me? English isn't my native language either.

 

[D.A.(Tony)Stewart]

Is it? 8x8 =64IO's=3x3bit = 6 bits parallel latch + R/W
or 8x8 SIPO register using 2 bit SPI + load
or 4:16 decoder x4 with SIPO latch

assuming all static digital out?
total bandwidth?
budget ?

 

[KlausST]

Hi,

please draw a sketch.

There is so much unclear. Like:
* DAQ .. usually means analog data acquisition. So "analog input", but you talk about "digital output". Maybe you have a special DAQ module in mind, then give a link to it´s datasheet.
* what does 8x 1 to 8 DEMUX mean? All DEMUX are controlled in parallel or individually?

And yes, all about digital levels, speed, available interfaces...
maybe also the analog side requirements: cross talk, ON resitance, OFF attenuation ...

Klaus

 

[Mancoba]

thanks for your reply and support. i have found a solution. I am just a beginner in digital circuit design... I have it on a sheet of paper. it looks a bit messy, but I hope you can understand my sketch. A two Part address of 3Bits + 3 Bits (CS) = 6 Bits in Total.

 

[D.A.(Tony)Stewart]

so you chose 3+3 bit IO for 1:8 x9 decoders to get 1 of 64 output ports selected.
Is that what you want? Or is there a memory bit or serial data on each port?

 

[KlausST]

Hi,

this currently is a 1 to 64 DEMUX using 9 ICs.

You could also use 5 pcs 1:16 DEMUX ICs.

***
But still the drawing is unclear.
It says DAC. A DAC is a digital-to-analog-converter. Digital input, analog output. But your sketch shows 8 outputs used as digital signals.

Klaus

 

[danadakk]

This is a SOC one chip solution. Note it uses most of GPIO so not knowing
your total design/schematic it could be revised to a family with more GPIO.

PSOC 5LP, depending on origin DAC 's data input. and other details. Possibly
PSOC 6 to get more GPIO for other functions.

Almost a codeless design you would need 1 start instruction for DAC.

Details such as speed, complete schematic of course need review.

Regards, Dana.

--- Updated Nov 28, 2023 ---

Note there is a lot of other stuff on this part, that you can use or ignore.

Multiple copies of many of these resiources. And for the adventuress one can
design your own resopuce using schematic capture of above and / or Verilog.

Compiler and IDE, PSOC Creator, free.


Regards, Dana.