Data sheet is not providing CL for GBW and SR op-amp specification

[Junus2012]

Hello

I wonder why foundries are not providing the capacitive load condition (CL)for the test of the given GBW and or transient behavioural like slew rate..etc

It is very known that GBW and SR are propotional to the CL, connecting higher CL for two stage amplifier will lead to different phase margin from the one plot by the datasheet or even to instability if the value of CL is large enough.

Thank you

Best Regards

 

[KlausST]

Hi,

What do you expect us to do?
No question, no datasheet, no example, no vendor...

Either you give useful information and a clear question, or the thread will be useless ... and deleted...

Klaus

 

[FvM]

You are referring to the OP library of a specific design kit? What is it? How is the OP characterized?

 

[Junus2012]

Dear friends, see the datasheet of the op-amp THP210

https://www.ti.com/lit/ds/symlink/thp210.pdf?ts=1598025092338&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTHP210

The GBW is given as 9.2 MHz. My concern is, since it is for sure multistage amplifier where the GBW is limited to the compensation capacitor, which is in turn relevant to the load for the given phase margin shown by the data sheet.

If a user connected a higher capacitive load higher, it will lead to degrading the phase margin.

So I would say providing an absolute value of the GBW without specifying the load condition is not the practical way. For example, the other opamp from texas instrument ( ths4271) giving GBW 1.4 GHz, again, the capacitive load condition is not shown in the datasheet.

https://www.ti.com/lit/ds/symlink/ths4271.pdf?ts=1598025454325&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTHS4271

So for the first glance It looks like the second op-amp is superior in GBW to the first one (and for sure it is), but might me they only reduced the compensation capacitor and that is it. If they did so, then the phase margin of the second amplifier will be less than for the first op-amp (THP210) for the same load condition.

That is my question and sorry to make Klaus angry

Thank you all

 

[dick_freebird]

If they do not provide the test conditions then
the datasheet is lame. But not uncommon,
that. Datasheets are often made my marketing
weasels who don't know what to ask, from
what's given by design or product engineering.
Conditions, particularly, are an afterthought
and where do you stop with the details?

Sometimes you find the basics in a single line
above or below the electrical tables for temp,
supply, maybe loading.

There may be deeper docs on the product
pages, app notes etc. which may allude to some
conditions in text or figures.

If not, then you go hit up the foundry applications
engineers and send them on an easter egg hunt.
Presuming your business matters enough to
them, to play.

Or put one on the bench and see what it does,
at -your -conditions - something that it probably
wants anyway.

 

[KlausST]

Hi,

Figure 12: Open loop Gain is shown with 50pF
Figure 13: Closed loop Gain is shown with 50pF

50pF is the maximum load capacitance without additional circuit. So both diagrams show worst case conditions.
Both diagrams show phase informations.

in 9.1.7.1 they say:
"Driving higher capacitive loads degrades the phase margin of the FDA, and causes instability issues. Best
practice is to perform a SPICE simulation using TINA-TI™ to confirm that the desired circuit is stable; that is, the
FDA has more than a 45° phase margin. "

Slew rate:
It is given with 15V/us. with the maximum load capacitance of 50pF this means just 0.75mA of capacitor current.
Maybe combined with the integrated slew boost circuit ... the slew rate may be guaranteed up to the maximum allowed load capacitance.

Klaus

 

[Junus2012]

Slorry I did mistake with the first datasheet

but the compassion still useful

Here the company gave the capacitive load condition, it is clear for sure given in figure 12 and 13

https://www.ti.com/lit/ds/symlink/thp210.pdf?ts=1598025092338&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTHP210

but here as I said the capacitive load is not the condition is not shown,

https://www.ti.com/lit/ds/symlink/ths4271.pdf?ts=1598025454325&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTHS4271

Now please let me continue with the first one, the op-amp that tested with 50 pF, The company shows an example of driving loads and feedback in terms of nF, such a value is far away from the maximum 150 pF, they could do by using a simple resistor in series as shown below

Thank you klaus for bringing me to that section

Thank you freebird for you commnet

 

[FvM]

All of the linked datasheets have full specifications of test conditions. In so far I don't understand the discussion.

Most characterising measurements of THS4271 are e.g. made with pure resistive load, clearly stated in the datasheet. You may want to see measurements with capacitive load, but that's a different thing than claimed lack of information about load condition.

This OP isn't designed to be operated with capacitive load, at best it can be driven through an isolation resistor as discussed in the capacitive load chapter.

I think that the question isn't optimally placed in the Analog IC design forum. You are discussing the behavior of commercial OPs without information about there internal structure, e.g. compensation scheme.

 

[Junus2012]

Most characterising measurements of THS4271 are e.g. made with pure resistive load, clearly stated in the datasheet. You may want to see measurements with capacitive load, but that's a different thing than claimed lack of information about load condition.

This OP isn't designed to be operated with capacitive load, at best it can be driven through an isolation resistor as discussed in the capacitive load chapter.

Dear FvM
Thnak you for your reply

That was my point, as you also read the datasheet showing the test with only resistive load. You claimed that this op-amp is not suitable for driving capacitive load without isolation resistor,

I want to adopt this idea from datasheet in the custom IC design, will it be possible to improve the phase margin of a two-stage op-amp by using small isolation resistor in series to a high capacitive load?


Thank you very much

 

[FvM]

"Not suitable to drive capacitive load" is at least valid if you are targetting to high signal bandwidths (e.g. > 50 MHz) these OPs are potentially supporting. A typical low impedance load in this frequency range is matched transmission line which is purely resistive. Please note that the feedback network capacitors in the low pass filter are not necessarily acting as capacitive load. Also the ADC driver topology has a built-in isolation resistor, thus the passive filter at the OP output doesn't cause stability problems.

The linked OP chips (medium bandwidth fully differential THP210 and high speed voltage feedback OP THS4271) are designed for general purpose with specific application focus, an IC design of your own would be optimized for your application requirements.

 

[Junus2012]

". Please note that the feedback network capacitors in the low pass filter are not necessarily acting as capacitive load.

Dear FvM

Thank you very much for your helpful comment,

I am interested on the status above, why this should be the case for the low pass filter?, if you assume the capackitor is an open circuit but this only valid for very low frequency while low pass filter can have fc in MHz

Thank you once again