[SOLVED] Cross-conducting half-bridge

[bubulescu]

Hello

I attached an LTspice schematic, a very simplified version of a MOSFET half-bridge driven by a push-pull isolated signal transformer. The FETs are cross-conducting, but their gate pulses are not overlapped. If I am getting things wrong, can someone please show me the error, why are they cross-conducting?

Even if the load and the output filter look very strange for the working conditions, they are a test and, if this problem is eliminated, they may as well have the final values as they are, so please ignore them (unless they are culprits).


Anticipated thanks,
Vlad

 

[D.A.(Tony)Stewart]

I don't have LSpice loaded here at the moment but I see you are using STD5NM60 , N-channel 650 V@Tjmax, 0.9 Ω, 8 A MDmesh™ Power MOSFET

The key factor is latency from input and output capacitance with driving gate & source resistance* capacitance in each case for turn off delay.

1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS

Equivalent output capacitance 50 pF , VDS = 25V, f=1MHz, VGS=0

In any case with unequal rise fall time thru the switch, you must create at least 1-3 us over temp.

Now compare with a better part.

AOD7S60
MOSFET N-Channel, Metal Oxide
Drain to Source Voltage (Vdss) 600V
Current - Continuous Drain (Id) @ 25°C 7A (Tc)
Rds On (Max) @ Id, Vgs 600 mOhm @ 3.5A, 10V

Coss 28 pF, VGS=0V, VDS=100V, f=1MHz

 

[Electro nS]

Hello
can someone please show me the error, why are they cross-conducting?

Vlad

i will put this the simplest way : 1- the signals driving the gates are not perfect , so the have rise time and fall time , so while the high side signal is falling the low side signal is rising , creating an overlap in the drive signals !!
2- even if your signals arenot overlaped and a deadtime circuit is inserted , another issue occur , it is the non-ideal behavior of a mosfet which has a capacitive gate , causing some time to turn on and some time to turn off , which causes crossconduction ..
Solution: insert enough dead time ... 500ns to 1us is enough for 20khz switching for example ...

hope that helps

 

[bubulescu]

Using the ST part was because that's what LTspice has in its default list and, while I agree that using a better part with lower charge and/or Rds would give better results (I couldn't find SPICE models for the A&O MOS you gave), the results are the same.

For example, among the things I have tried:

- giving up the signal transformer and using brute G-sources (with parallel resistances), while making sure there is no cross conducting driving pulse (which it isn't, even now)

- increasing the already existent dead-time from 50ns (switching frequency is 400kHz) to 200ns or more, also making sure there are no cross-conducting driving pulses

- using lower Vcc (from 300V to 30V) and using 6nC/6mOhms NXP FET (from default database), while making sure the two previous changes fit the needs (no cross-conducting gate drive, etc). This change, for example, shows the FETs conducting while the gate pulses go negative(!!!).

I might add other minor things such as removing Cpar from the supplies, leaving only Rser, or adding ideal diodes to gate-source with ".model d d Vrev=12" (an ideal Zener), etc.

After all these changes I still get cross-conducting even though there is a considerable gap between the gate pulses. Sometimes (see change #3) I get both FETs conducting when it's impossible for them to conduct. At this point I decided to ask for help.

Therefore, while I'm not dismissing your answers, I really say you should base them on the schematic I have given.


Vlad

 

[D.A.(Tony)Stewart]

Consider that cross-conduction from Coss RdsON is unavoidable, unless you skew your gate timing to have at least 1us deadband. I suggested more earlier.

 

[bubulescu]

True, but the models in LTspice are limited. Besides, I also omitted the effect of the large filtering inductance (30mH), V(x) wouldn't go low with Vgs.

Do you, by any chance, know of a high-voltage, high(er)-speed MOSFET model for SPICE? It doesn't have to be high-current since I'd be dealing with a maximum 100mA, but the voltage may need to go to 300V..400V, at least. I would only need one model to test the waveforms, who knows, maybe I couldn't even afford in in reality

 

[D.A.(Tony)Stewart]

I wouldn't reply on SPice models too much as layout is not included with stray capacitance, ESL, ESR and ground plane.

BUt read this and consult with Diodes Inc who bought Zetex long ago, my fave company for low RdsON and lowest Rce.

**broken link removed**

THere ought to be hundreds of parts that meet your requirements, whatever they are.

 

[bubulescu]

I, for one, prefer NXP, or Fairchild, but they don't seem to have what I need now. I went to DiodesInc and they have a nice list of models, but there aren't too many high-voltage high-speed NMOS. There are a few, though, and their models seem reliable enough, for example, ZVN0545G has Rds=50, which is a bit scary, but it also has Coss=10pF. I think I might actually have to increase the output inductance, now, to get proper dissipation levels.

At any rate, the result is that now I get much better waveforms with the original, full schematic (which has proper driving, feedback, snubbers,etc). There's still tweaking to be done but, this time I'm on the right path.


Thank you for the guidance,
Vlad

 

[mtwieg]

Keep in mind that the effective Coss is hugely variable as a function of the drain voltage, so don't just look at the one Coss number given in the table. Look at the actual plot of Coss vs Vds. Ultimately what you want is a low Qoss, but that's never plotted in the datasheet.

 

[bubulescu]

Yes, but Coss usually drops with Vds. Unfortunately, the datasheet for this ZVN0545G in particular, doesn't show any graphs, in fact, it seems too few from DiodesInc have. Still, the results seem to be good now, I'm getting no cross-conduction and ~25mW/FET, instead of the 400mW+ (in the good cases) before. The dead-time needs polishing, now.

 

[schmitt trigger]

Cross conduction is a fact for real world bridges, and must be planned accordingly.
Most designs include a forced deadtime between the two Mosfets. Meaning that you ensure that the Mosfet that is currently on, will be turned off prior to the Mosfet which is off is now turned on.

The circuit can be as simple as a resistor in series with each gate, and a schottky diode in parallel with the resistor (with the anode looking towards the gate).

 

[bubulescu]

This is why I provided the schematic for LTspice, so anyone can see and run the simulation, thus having all the answers beforehand, like the already present dead-time (also mentioned in #4). This way, IMHO, all the answers will be based on facts rather than theory and assumptions.