create testbench for counter (Xilinx ISE10.1)

[popoyboys]

hi everyone,

i am new to VHDL and i am just starting to learn thru the quickstart tutorial that comes with the software. (Xilinx ISE 10.1)
may i ask how to create a testbench from this vhdl code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitive in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;

 

[TrickyDicky]

all you need to do is create an entity (probably called counter_testbench) that instantiates your counter. It doesnt have to have any inputs or outputs, it just stimulates the IO on the counter entity. Because you will only be simulating it (not synthesising) you can do all sorts of stuff thats not synthesisable:

eg:
signal clock : std_logic = '1';

...
clock <= not clock after 10 ns; --50MHz clock.

 

[pini_1]

You might want to look on some test-bench examples. For instance:

"VHDL IP Stack
This project implements the lower layers of a standard TCP/IP stack based on a free code from University of Queensland: IP stack
My first steps to understand the project, after reading the documents are:

Adjustments to the code in order to have it compiled using the free VHDL simulator GHDL. code ..."

**broken link removed**