Conversion Error with conv_signed

[ghostridergr]

Can anyone help me in that:

 read_inp: for k in 0 to N-1 loop
             a(k)<=to_stdulogic(a_var(k));
           end loop;
              wait for 1 ms;
            inp1(1,1)<=conv_signed(a,N-1);

where it is:

signal a,b: std_logic_vector(N-1 downto 0):= (others=>'0');

The compiler complains "No feasible entries for conv_signed". But as i see in std_logic_arith it can take as argument an std_ulogic. What i 've done wrong?

 

[TrickyDicky]

dont use std_logic_arith, use numeric_std.

Then it will be a bit clearer.
Any reason you need a std_ulogic rather than a std_logic?

 

[ghostridergr]

dont use std_logic_arith, use numeric_std.

Then it will be a bit clearer.
Any reason you need a std_ulogic rather than a std_logic?

yes but if i use numeric_std which the function to_signed doesn't as an argument std_logic_vector. Thats why i used ulogic, so as to do the conversion with conv_signed. What changes do you propose?

These are my imports:

library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

 

[TrickyDicky]

you easily convert between std_logic_vector, signed type and integer with numeric_std

 

[ghostridergr]

you easily convert between std_logic_vector, signed type and integer with numeric_std

Thanks, I got it!