hcu
Advanced Member level 4
Hi,
This is about the axi3 interconnect. Here , In my SoC there is a axi3 interconnect with two masters A and B. where A is a CDMA and B is a processor .
And only one axi slave is connected to this interconnect.
The issue is, when the master B requests a data from the slave. then there is no problem the axi3 interconnect taking the data from the slave and directing the data to the Master B only.
but when the Master A initially performs some operation and completes it successfully, now if master B requests any data from the slave then the axi3 reading the data from the slave and offering it to Master A but not for Master B. It's like the master A (CDMA still holding the bus). how to avoid this situation. Here the CDMA(master A) is custom written , and axi3 and others are dw components.
Any idea ?
regards,
hcu
This is about the axi3 interconnect. Here , In my SoC there is a axi3 interconnect with two masters A and B. where A is a CDMA and B is a processor .
And only one axi slave is connected to this interconnect.
The issue is, when the master B requests a data from the slave. then there is no problem the axi3 interconnect taking the data from the slave and directing the data to the Master B only.
but when the Master A initially performs some operation and completes it successfully, now if master B requests any data from the slave then the axi3 reading the data from the slave and offering it to Master A but not for Master B. It's like the master A (CDMA still holding the bus). how to avoid this situation. Here the CDMA(master A) is custom written , and axi3 and others are dw components.
Any idea ?
regards,
hcu