common constant in files of a project

[ahmadagha23]

Hi
I have many constants in my VHDL code, which are used in some source code
files in my activhdl project. how can I define these common constant in a seprated file(pakage) in my project and use them in other files? Please describe the method for me.
Regards

 

[farhada]

It is simple, you have already answered to your question.

Create a package file, put all your constants in it, then add the following lines in your code

library work;
use work.mypackage.all

in all your vhdl files right after the IEEE library lines.

Best regards,
/Farhad Abdolian