sudhar_v
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Hello all,
I am trying to simulate a class AB output stage similar to the one by Huijsing (JSSC 'Dec 94), with a single supply.
VDD is expected to vary between 3V and 5 V. When I run AC analysis in spectre the amp looks stable at lower VDDs (say upto 4V). At higher VDDs(4V and any voltage beyond) the phase flips 180 degrees(see attachment), as if there is one less inversion through the op-amp. I am trying to look at the DC operating points and see what is changing. The magnitude also varies somewhat as VDD is swept. Transient sims seem to correspond with AC. It looks like the PMOS and NMOS alternately push and pull current through output, unable to find a bias point for their gates. This does not happen at lower VDDs.
I was wondering if anyone has seen this happen during AC simulation. I would appreciate any pointers on trying to understand what may be happening. Thanks!
I am trying to simulate a class AB output stage similar to the one by Huijsing (JSSC 'Dec 94), with a single supply.
VDD is expected to vary between 3V and 5 V. When I run AC analysis in spectre the amp looks stable at lower VDDs (say upto 4V). At higher VDDs(4V and any voltage beyond) the phase flips 180 degrees(see attachment), as if there is one less inversion through the op-amp. I am trying to look at the DC operating points and see what is changing. The magnitude also varies somewhat as VDD is swept. Transient sims seem to correspond with AC. It looks like the PMOS and NMOS alternately push and pull current through output, unable to find a bias point for their gates. This does not happen at lower VDDs.
I was wondering if anyone has seen this happen during AC simulation. I would appreciate any pointers on trying to understand what may be happening. Thanks!
