can you shield clock with VDD & VS both

[atlaakreddy]

can you shield clock with VDD & VS both

 

[KlausST]

Hi,

Why do you want to shield it? Impedance control, EMI, EMC..?
Sure you are talking about "inside an IC"?

Klaus

 

[HasHx]

if for EMI you can't as you need to make a valid path for the return loop.

 

[atlaakreddy]

iam asking cts level in terms of physical design(vlsi)

 

[dick_freebird]

What you call "shielding" may in fact be unacceptable clock
branch loading. Cut radiated emissions but push more current
spikes into the power/gnd planes (or more likely, the spindly
little busses you see in Big Digital cell libraries).

Maybe you'd be better off routing complementary clock pair
and criss-cross it every so often so that "far" field common
more emission is first-order nulled.

You could make a fully enclosed transmission line structure
if you cared to burn the layers and area. But now your clock
load impedance is very low, and stubs may still emit at a
significant level.

If you are worried (say) about contaminating the "little RF"
with the "big D" there's nothing like distance (physical, and
electrical) to help with that. Look to the current loops and
how longitudinal currents may cause magnetic, as well as
EM, coupling.

It's black art, if there was an easy answer it'd be well known.

 

[ThisIsNotSam]

iam asking cts level in terms of physical design(vlsi)

you can. it helps "some" with timing, but sacrifices significant silicon real state. a better alternative could be to use a mix of shielding and spacing, as well as layer assignment. really depends on the design and how much you care about crosstalk.

ps: this question should be in the digital asic portion of the forum