Cadence Schematic - How to detect a floating 'input output' gate?

[fooliojp]

Hi,

We recently discovered two transistors connected together via their gate terminals. The connecting net only connects from gate to gate and nowhere else in the schematic. Unfortunately the gate pins for these two transistor devices are defined as direction 'input output'. Therefore the Cadence schematic check does not flag them as floating. If the pins were defined as input pins then this floating connection would have been flagged as there is no input to either gates.

Is there a way I can detect this circuit condition using Cadence's provided checks or a custom SKILL check?

Thanks in advance

 

[antlhem]

Is there a way I can detect this circuit condition using Cadence's provided checks or a custom SKILL check?
Thanks in advance

Can you provide a schematic? Usually Cadence will show you the flag when you click on 'check', it show how many pins or wires that are not connected.

 

[dick_freebird]

You could put the PDK transistors inside a
schematic / symbol pair of your own making,
and make the gate terminal of -that- an
input.

You could copy the PDK device local and
edit its symbol pin type property to "input".

SKILL, I got nuthin'.

 

[Dominik Przyborowski]

In theory is possible to create schematic rule which flags it. The problem is, noone drive Cadence to documented SRC enough with good examples.

One of the alternatives is to perform one of the spectre checker, like floating node check and look for the results. It needs short simulation but gives you a list of only gates connections in circuit.