Altera RAM clock edges? (M9K in Stratix IV)

[std_match]

In the Altera example timing diagrams, they always change address/data on the falling clock edge, and the RAM does it's job on the rising edge. I would prefer to clock everything on the rising edge. I can't find any discussion about this. Of course, the address/data hold times will be worse, but I can't find any warning against that method.

All suggestions are welcome!

 

[FvM]

The timing diagrams are only simplified for clarity, I think. In a ususal synchronous design, all input signals to the RAM block would be sourced from registers also clocked on the rising edge, changing it's output a short time after the risidng edge. Of course, they work perfectly, as they do in other places of the design.

For FPGA generated signals to the RAM, the timing analyzer is watching about setup and hold times. In case of external signals, you may want to create a larger timing margin. In this case, changing of signals on falling edge may be reasonable, of course.

 

[std_match]

Thank you for a good explanation. I am used to designing "normal" hardware, where you have to check the setup/hold times between all components.
It seems to be a little different when designing circuitry for an FPGA. The tools will automatically check the timing.

My conclusion is that I should not worry about hold times (unless I put logic on the clock line). This means that I can clock everything on the same edge.
The setup times will automatically be used to calculate the maximum clock frequency.

 

[FvM]

Yes, I agree. Using this standard synchronous design method, you can achieve a maximum clock rate with a given device family.