samcheetah
Advanced Member level 2
lpm_shiftreg xilinx
I am porting a design from Altera to Xilinx and the design uses the lpm_shiftreg with a serial input and parallel output. I have looked at the Xilinx LogiCORE RAM-based shift register but the problem is that it doesn't have a serial input.
Can someone point me in the right direction?
I am porting a design from Altera to Xilinx and the design uses the lpm_shiftreg with a serial input and parallel output. I have looked at the Xilinx LogiCORE RAM-based shift register but the problem is that it doesn't have a serial input.
Can someone point me in the right direction?
