purplestar
Newbie level 4
Hi ,all
For converting phase noise to jitter, there is a frequency range for integration, and I find the following statement in ADI doc.
"Generally speaking, the upper frequency range for the integration should be twice the sampling frequency, assuming there is no filtering between the oscillator and the ADC input. This approximates the bandwidth of the ADC sampling clock input."
i want to know why 'the upper frequency range for the integration should be twice the sampling frequency' for ADC???
THANKS
For converting phase noise to jitter, there is a frequency range for integration, and I find the following statement in ADI doc.
"Generally speaking, the upper frequency range for the integration should be twice the sampling frequency, assuming there is no filtering between the oscillator and the ADC input. This approximates the bandwidth of the ADC sampling clock input."
i want to know why 'the upper frequency range for the integration should be twice the sampling frequency' for ADC???
THANKS