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A frequency synthesizer using a PLL for an undergraduate project

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Funkymix89

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Hello everyone,

I hope I posted this under the right topic.
Please excuse me if my English isn't so good, because it's not my first language.
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My fourth year undergraduate project is to build a simple frequency synthesizer using a phase locked loop ( probably with a divide-by-N block in the feedback route ).

The purpose of the project:

Our lab at the college has a pretty low frequency signal generator ( ~20Mhz sinusoid/square wave ). My professor/advisor told me to build a device which converts this 20Mhz into the 2xx-5xx Mhz range,
so as you can see, my project doesn't require some sort of frequency step between frequencies because the reference signal that enters into the phase detector is the signal generator itself, which is tunable.

I want to build the phase locked loop from discrete components which are :

- a Phase Frequency Detector (PFD).
- a Charge Pump (CP).
- a VCO.
- a comperator ( because the VCO's output is sinusoidal and I want to work with square waves).
- a divide-by-N block which I think will be implemented with a digital counter.


I've read a lot of theory and math about Phase Locked Loops. The part about the circuit design is the part which scares me, because I don't have any experience with circuit design.

I opened this thread because I'm looking for some guidance/help with the project,
so can you please help with some reading material or simulation tools, which components to use, and can you also tell me if my project is realizable from these discrete parts?

thank you very much,
David.
 

Hi Funkymix89

If you do not know circuit design this project is top for you. To be honest i have some circuit design background but when design PLL I have a lot of problem with it. Maybe someone can help him?
 

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