5V power clamp with 0.25um technology for ESD protection

[alpha999]

power clamp esd

Hi,
I'm looking for a power clamp operating between GND and 5V for independent rail based ESD protection. (There are other supplys available, like 3.3V and 2.5V)
The technlogy is 0.25um.
An RC-Triggered NMOS clamp for 2.5V was successfully designed, but how to scale up to 5V ? Has anybody an Idea ?
Best Regards,
Alpha999

 

[mdcui]

define clamping in cmos

in our process, we stacked two mos transistors which can tolerate 2V operation range to be a 4V tolerate clamp, which is similar to your problem, in this clamp, the discharge path is through two serial connected mos transistor. and with an extra RC timer to control discharge timing, very efficient. much better than using the high voltage device to do clamp since they are really huge.

 

[alpha999]

rc triggered esd clamp

Thanks. We don't have any power devices at all so we have to take the small ones.
Do you have any picture or reference of the whole circuit ? How did you connect the RC trigger to the High voltage ? And how where the big mos put exactly into schematic ?

 

[ESDSolutions]

esd clamp

Hi alpha999

Before you start desiging a new 5V power clamp you should find out some requirements for this clamp. Most important is to define the so-called ESD design window. There are 3-4 main questions to define this ESD design window

- What ESD specification do you target? The standard 2kV HBM? Some MM requirement? Or do you have high ESD protection requests like currently is being asked for HDMI pins (>8kV HBM component level). This will define the minimum ESD current level to be shunted away from the pin.

- What circuit needs to be protected by this clamp? Are these all cascode - series connected MOS transistors? Do you have any IO circuits within this domain that needs protection? This will define the maximum voltage drop allowed over the ESD clamp.

- What are the signal characteristics? Is it a 5V DC power supply or will the voltage at the pin vary between 0 and 5V. Is this a so-called overvoltage tolerant pin? This will define the minimum trigger voltage.

- How can ESD be detected? What is the frequency of the signal? Can you rely on RC schemes to detect ESD or can you use voltage based detection? Is there any information on power up sequences?

- For ESD clamps you also need to worry about latch-up. The latch-up risk very much depends on the application.

Let me know if you need further details or support. If this is a standard CMOS technology and if you cannot risk to iterate /re-spin this IC you might look into hiring a consultant. I have good experience with the people from Sarnoff Europe. They have a strong track record with many customers worldwide and can certainly help you out in a short time (few days) at a low cost and are endorsed / supported by the major foundries.

ES

 

[alpha999]

3.3-v 0.25 um cmos technology.

Hi ES.
Thanks for your answer and sorry for my inexactly question.

- ESD Target is CDM and HBM wheras everybody will be happy at the end if we reach the lowest acceptable class (one higher than the 0-150V class)
- In the 5V domain there are mainly bipolar transistors as well as cmos transistors
- The 5V pin is ja a single DC input pin. Rise times for power up sequencing can be controlled easily.
- There are no IO pins related to the 5V, it's just a single power supply.

All other supplys (2.5V and 3.3V) and pins have always diodes to vcc and gnd, and each has RC-Triggered NMOS clamp.

- ESD consultants -> I will think about it.