chenyiqun0523
Newbie level 1
Hi guys,
I need some help to generate a 1024-point FFT core on Xilinx Virtex 6 FPGA.
I have 32 incoming data samples per clock cycle but the Xilinx FFT IP core only support up to 12 channels which means the core only take 12 samples per clock cycle.
I have tried increasing the clock frequency so that the FFT core can run faster than the sampling rate. However, since the clock is already running at 225MHz, I can only double it to 450MHz.
I have been thinking about using Cooley-Tukey algorithm and parallel four 256-point FFT cores with 8 channels each but the architecture is going to be very complex.
Any good idea to solve this problem?
Thanks!
I need some help to generate a 1024-point FFT core on Xilinx Virtex 6 FPGA.
I have 32 incoming data samples per clock cycle but the Xilinx FFT IP core only support up to 12 channels which means the core only take 12 samples per clock cycle.
I have tried increasing the clock frequency so that the FFT core can run faster than the sampling rate. However, since the clock is already running at 225MHz, I can only double it to 450MHz.
I have been thinking about using Cooley-Tukey algorithm and parallel four 256-point FFT cores with 8 channels each but the architecture is going to be very complex.
Any good idea to solve this problem?
Thanks!