Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How a substrate connection near source of the CMOS transistor reduces the latch up?

Status
Not open for further replies.
C

chandrarao

Newbie level 4
Joined
Jun 12, 2007
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,329
Can any one explain how a substrate connection near to souce of the CMOStransistor reduces the LATCHUP.
 

Re: Regarding LATCHUP

hi
it will reduce the resistance so current requirment to trigger become more

there by reducing latchup

one more reason is that when u connect pmos substrate to VDD the gate of pnp is getting +ve supply so it will prevent hte swithing on

regards

analayout
 

Re: Regarding LATCHUP

chandrarao said:
Can any one explain how a substrate connection near to souce of the CMOStransistor reduces the LATCHUP.
Click to expand...


there are 2 bjt in a latch up model. PNP and NPN. in the model, the substrates/well are connected to the bases of the BJTs. if there is enough voltage drop in the wells, there is a possibility that these BJTs are triggered because these wells are directly connected to the their bases....if they are triggered, latch up occurs... one way to reduced these voltage drop is to lessen the resistance in the well/substrtate. but how do u do this? just put enough contacts or bias to the wells, and not just near the source.
 
Re: Regarding LATCHUP

latch up is generally trigrred when their is a spike( can be noise) at the power supplies happen.
now if you have substrate connections at the source, then the noise pulse will alredy have a low resistive path to ground, thus preventing to develop any potential that can cause latchup.
 

Regarding LATCHUP

u can search on book
 

Regarding LATCHUP

keep the PMOS and nMOS in some space to avoid the latch up.

when place the layout, you can refer the design rule for detailed information for preventing latchup
 

Re: Regarding LATCHUP

Putting NMOS in deep-nwell will solve latchup issue
 

Re: Regarding LATCHUP

In CMOS logic a SCR( back to back NPN & PNP structure) is formed and when it triggered ON there is a huge current from VDD to VSS(nearly short ckt). It can be avoided by using substrate contact...because these contacts are n+ (PMOS) or p+(NMOS) these provides a low resistance path towards VDD or VSS reducing the currents flowing in SCR which prevents it from triggering.
 

Re: Regarding LATCHUP

It should be many substrate connection. It decrease the resistor. And it also can absorb the minor carrier.
 

Re: Regarding LATCHUP

I think very sensitive block should be surrounded by N+ guard ring and P+ guard ring in RF circuit or others. Deep n-well is used to reduce the noise.
 

Re: Regarding LATCHUP

if you have a background in layout, we all know that the things you've said are correct but it's better if someone put an illustration for easy understanding. tnx in advance.
 

Regarding LATCHUP

can anybody explain hoe butted contact help in preventing latchup.
 

Regarding LATCHUP

u can see allan hating book of analog layout

Added after 2 minutes:

there also book of chen where latch up is given in very good manner.
 

Re: Regarding LATCHUP

chandrarao said:
Can any one explain how a substrate connection near to souce of the CMOStransistor reduces the LATCHUP.
Click to expand...

Hi Chandrarao

The substrate taps are heavily doped (P+ /n+) which means they act as a low resistance path for any leakage current in the substrate thereby inhibiting the formation of voltage required to trigger the parasitic transistors formed, thus avoiding latch up.
I believe this helps.

Regards
Brittoo
 

Regarding LATCHUP

nicely describe in n weste book
 

Re: Regarding LATCHUP

A fact is that the substrate has some resistivity.Although it is tied to a ground,in its
other position , voltage will be higher than ground because of the current flowing through the substrate.when this voltage exceed the adjacent PN junction ,this junction will foward biased.Now if this PN juction is a pasitic bjt' emitor ,this bjt will
open ,it will added to the propability of latch up occurance.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top