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At speed test for DFT ?

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feel_on_on

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at-speed dft

hi,all

the flow as following :
1. synthesis ,compile a design
2. insert scan chain,write a spf file
3. insert occ controller for DFT test, write spf file

is the flow correct ? anyone can give me some advice!

Thanks
 

what is at-speed testing in dft

wait for dft_guy reply me
 

at speed dft what is it

feel_on_on said:
hi,all

the flow as following :
1. synthesis ,compile a design
2. insert scan chain,write a spf file
3. insert occ controller for DFT test, write spf file

is the flow correct ? anyone can give me some advice!

Thanks
Click to expand...

this flow is same as normal scan insertion !!
at-speed must be different ...rite ! i am nt sure abt AT-speed ! luking for others reply !
shiv
 

tft+dft

I have to plead some ignorance here, because I have not used this flow. But if you go to Solvnet and read what documentation is there, it seems that using the OCC (I assume this means On-chip Clock Control) requires very little more than just some extra configuration commands - you insert_dft as normal, and write a test protocol. The flow is optimized for DFTC->TetraMAX. TetraMAX creates at-speed scan patterns.

John
DFT Digest
 

dft speed test

thanks for all guy's reply.

but ,how to do At-speed test by you?

write a clock controller or any other tools?
 

atspeed testing

We write the OCC by hand, i don't think the OCC generate will work well, you should know how OCC
work. Mentor has some paper on their web , you can find some useful in those paper.
 

at-speed dft tft

Hi,

Can you please expand the abbreviations used in your post to make it more clear. At speed DFT is a technique used to test the circuit at normal speed of operation, whereas, in general the testing process uses a slow clock instead of functional clock.

feel_on_on said:
hi,all

the flow as following :
1. synthesis ,compile a design
2. insert scan chain,write a spf file
3. insert occ controller for DFT test, write spf file

is the flow correct ? anyone can give me some advice!

Thanks
Click to expand...
 

dft what is at-speed test

what is At-speed test?
 

tft speed test

Check out this article - it has the basic concepts!

**broken link removed**

John
DFT Digest
 

at speed testing dft

In DFT there should be ATPG, TFT mode.
TFT mode is the at speed test, not the full speed test. In TFT test, U should employ PLL to generate at speed clock. generally use SCAN_EN to switch shift_clk and lauch/capture clock. actully the lauch/capture clock is the highest frequency in the design. U can connect the DFT tool vendor, they will teld u.
 

at speed test occ controller

hello,

I have insert OCC controller into my design for at speed test.But some register inside OCC controller were non-scannable.please
tell me how to make clock controller itself scannable for At-Speed testing

please reply me as soon as possible.Thanks a lot.
 

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