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Swithing Regulation question

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ilter

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Dear all,
I have some questions.
1.I design swithing regulator.Do buffer need to add between nonoverlap circuit and power mos?
2.How do I decide power mos's length.
3.If I use one regulator and LDO in parallel. Sometimes LDO is on and Sometims SW is on. If LDO is on and SW nmos is off , is it ok? Which thing do I take care?
4.LDO need one capacitor to compensation. If my output current is bigger, my esr is smaller then phase margin is better? why?
Thanks very much?
 

(1) yes, you need ,because the great gate-cap of pass transistor.
(2) as short as you if process is permited
(3) ok
(4) how about your op in LDO?
 

paley said:
(1) yes, you need ,because the great gate-cap of pass transistor.
(2) as short as you if process is permited
(3) ok
(4) how about your op in LDO?

"A" means error amp and buffer in my picture.
 

I am learning about buck regulator.
How much current is enough to control power FET with given Qgs and Qgd?
 

Thanks you!
I have another question: How do I calculate Qgate of power MOSFET with Vds?
Ex: Qg=4.5n with Vds=10v(datasheet)
Qg=? with Vds=5.5v?
 

your idea is good.
 

Calculate Qg in this way:
Qg = Cgs*Vgs + Cgd*Vgd + Cgb*Vgb in my understanding.
 

Sorry for my late response. Did you find the answers you needed in the app. notes? If not, let me know.
 

Thanks inventor!
My friend said "for most power MOSFETs the appoximation can be useful:
Cgd=2*Crss1.sqrt(Vds1/Vdsoff)"
Is he right?

Added after 1 minutes:

sorry, i mean Crss1 is Crss at Vds1(datasheet)
 

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