wHY WE HAVE CODE AND DATA SECTION .

code section data section

why do we have code and datasection seperately

small data section

hi,

in which processor?

its coz the code section must be write protected, and any overwriting of code with data would yeild junk code... system failure

if u're asking about DSP processors where the data and code bus, and hence code and data memory r different. its for performance.( dual access per cycle)

code section data section of a program

The keywords you are using depend on a processor architecture.
But generally a code section is were the instructions for the CPU are located.
The data section can reside either in the data memory RAM or in the program memory. There are a lot of microcontrollers which are based on Harward architecture, where the program and data memory buses are separated.

what is code section and data section

Hi, Its more efficient to have a special code and special data section: Why ?. most processors fletch the unstructions from code memory while processing code fletched before, this pipline type of thing is most effective if its not stalled by cycles to excess data through the same bus therfore most processors today have two internal busses, one for code and one for data. The second thing is that the width of the busses can be optimized for the type of work. 32 bits wide data bus on a DSP with maybe a 16 bit wide code bus so that one clock can fletch two instrucytions from 32 bit memory per clock cycle etc... So you see its only for speed and efficiency. The early processors, like the 6802 used the same bus and did not have a pipeline, Intel 8088 and 8086 has pipelines and two busses too. regards, Paul.

code section and data section

Some processors allow code and data to be intermixed. But this usually means the memory is external and the micro has a bus and uses logic chips to select the appropriate blocks of memory that the data and code are in. Typically, the code is in some kind of non-volatile memory while the data is in ram. But this is a complicated system, especially when you are trying to use a umicro that uses as few pins and support chips as possible and fits on as small a board as possible. So, put the code and data onboard the chip. Since the data will be in ram (and yes, maybe EEPROM) and the code will be in FLASH or some kind of ROM chip. It is a reflection of the fact that micros are everywhere nowadays whereas when they first started out they were reserved for very expensive boards, and noone minded the glue logic that was needed to be used to interface to the memory.

code section+data section

Is your question about processor architecture or about data and code section definitions used by compiler/linker ?

data section code section

Hello,

in processors with Harvard architecture Program Memory (PM) and Data Memory (DM) are separate and each one has a dedicated bus for IO operation to/from other functional units: this allow the parallel fetch from the 2 memory areas of Operand (from DM) and instructions/operand (from PM) in one clock cycle.
This architecture is at the basis of some Analog Devices DSP families (21xx, SHARC) where this feature is exploited to perform a MAC operation (multiply and accumulate) in one CPU clock by loading the ALU registers with the two operands fetched from DM and PM at the same time.
A tytpical example is FIR calculation loops, which are made up of loops with iteration of asm instruction line (taken from ADSP-2181 code) like follows

MR = MR+MX0*MY0(SS), MX0 = DM(I3,M0), MY0 = PM(I6,M4);

This asm line codes the following operations (executed in a single clock cycle)

1) multiply and accumulate MR += MX0 * MY0
2) load MX0 with Data Memory word pointed by address register I3 which points to a sample buffer element
3) increment the pointer by the value set in M0
4) load MX0 with Data Memory word pointed by address register I3 which points to a FIR coefficient array
5) increment the pointer by the value set in M4

In particular the single clock execution is possible because DM and PM accesses happen through separate bus and read/write from/to memory is performed on different clock phases in the same cycle (read first then write).

Regards
Mowgli