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Question about Keying (ASK, FSK, PSK)

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reyge

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In the demodulator side, should the period of the input ( or the duration of one message) be given?
Is it necessary that the output should be equally spaced in time like that in the input of the modulator?
I'm having some problems during the shift from one frequency to another in FSK or, in other words, the boundary between two different input data... thanks
 

ya the demodulator should be aware of the input time slot... but in the case of FSK if a PLL is used for demodulating then it is not necessary that it should be aware of the input time slot unless the other frequency used is not in the PLLs capture range........



Can u specify what u r using for demodulating the FSK signal.........
 

I know that the PLL can "lock" a signal.. But can you explain how the PLL can know the input time slot?
 

when the FSK changes the frequency the PLL automatically captures the new frequency if the new frequency is in its capture range and there is no need for the PLL to be aware of the time slot to do this because the PLL is constantly tracking the channel......
 

ah i see... but then when FSK changes frequency, it is possible that there are intermediate frequencies before the final frequency is attained. During that time, the PLL also captures the intermediate frequencies which can be undesirable because these frequencies can represent an input... But if the input time slot is given, i may be able to do something about it...

By the way, i'm trying to implement an all digital 8-FSK demodulator

thanks
 

i accept there would be a intermediate frequency during transition but the PLL is fast and if the transition is fast enough this intermediate frequency wont introduce that big an error........
my friend was implementing an FSK and if he has details corresponding to yours i'll get it for you........
 

oh i got your point. I hope your friend has a good material.. my PLL seems to be slow...
Is there any criteria on the frequency of the carrier signal with respect to the input time slot?

thanks
 

my friend has implemented using time slotted one only and that too BFSK only.... but the criteria for the carrier frequency is that they should lie within the capture range of the PLL....
 

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