Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Fixed Point division in VHDL

Status
Not open for further replies.
I

info_req

Member level 5
Joined
Jun 20, 2007
Messages
81
Helped
6
Reputation
12
Reaction score
4
Trophy points
1,288
Location
Pakistan
Activity points
1,764
Hello dear,
I need algoritm/ guideline on fiexed point division in vhdl.
Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).
 

'paper and pencil' method is easy to design
you can google it
 

    I

    info_req

    Points: 2
    Helpful Answer Positive Rating
info_req said:
Hello dear,
I need algoritm/ guideline on fiexed point division in vhdl.
Secodnly, how to check that in how many cycles FPGA performs an operation(i.e. +, -, / etc.).
Click to expand...

we al know the pensil and paper method. Can someone explain to us/me how to check the number of cycles an algorithm needs ?
thanks in advance.
 

can't be used lmp in stand ??
 

There're a lot of algorithms available for division in Hardware.

Try the Newton Raphson Algorithms.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top