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Help me design an inverter which will maintain the same duty cycle

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DZC

DZC

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Hi all,

I want to design an inverter.
The first-line requirement is to maintain the same duty cycle.
Then,what shall I pay attention to?
Will the bigger size help to get over the process error?

Thanks for your kind-hearted suggestion.
 

Inverter design

Hi
select (PMOS size / NMOS size)=Up/Un
Up and Un are mobility of P ans N.
regards
 

Inverter design

Hi
to get equal rise/fall time, U can select size=Up/Un;to optimum power and performance, U may set the size below Up/Un
segment big devices into small segment of less than 3u. This is critical to annotate in schematics so Parasitic extraction work correctly (more close to layout) in pre-layout simulations.
regards
 

Re: Inverter design

have a look at this thread also...
 

Inverter design

go thr baker book
 

Re: Inverter design

DZC said:
Hi all,

I want to design an inverter.
The first-line requirement is to maintain the same duty cycle.
Then,what shall I pay attention to?
Will the bigger size help to get over the process error?

Thanks for your kind-hearted suggestion.
Click to expand...

Just being it is simple digital block , you have to look into Tr/Tf = C1 * Wp/Wn
where C1 is constant just ignore constrate on Tr=Tf for 50% duty cycle assuming
Wp = 2-3 * Wn (get accurate from simulation )

next Drive this merely depends on Width and is directly proportional
 

Re: Inverter design

Hi,
If you are simulating the inverter
connect the output with the input (physically or virtually ) then try to adjust the aspect ration until the voltage of this point (input tied to the output) is equal to VDD/2
Then you have same strength PMOS and NMOS, it will keep the same input duty cycle if you use even number of successive inverters, or (1-Duty Cycle) if you have odd number of successive inverters.
Try it & tell me the results
best regards,
Rania
 

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