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As the input goes from vss to vdd or vdd to vss, one stack turns off and one stack turns on. Before one turns on and the other shuts off there is a period of time when both are on.
The 'crowbar' effect is there to shut down the device when it detects excessive current or the current goes over the maximum allowed. It protects itself and shuts down untill power is removed and has a change to cool down (reset). Many devices have the same protection including the good old 2N3055...
In general crowbar means
a Circuit used to protect the output of a source from a short circuited load. Load current is limited to a value the source can deliver without damage.
Yes, crowbar is a term used in power supply design, where a circuit (SCR or some other device) is used to short power and ground and blow a fuse or other protection scheme to kick in, rather than allow over voltage or voltage spikes to propagate.
A crowbar power in reference to CMOS, is as mentioned before, a condition when both NMOS and PMOS stack is turned on creating a high current draw condition. This is especially bad in large output drivers and smart I/O circuit designers typically try to avoid this.
As stated by cl_mos, this happens while the input to a cmos gate is swithing between states.
crowbar current in the current from vdd to vss during transition of the gate. There is a time, where both, NMOST and PMOST is open. This crowbar current is a real problem in power dissipation and a much larger problem in EMC issues, when they have a large dI/dt --> compare slew rate controlled output buffer, some of them use a break before make structure to avoid crowbar currents.
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