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Internal Dual Port RAM interface

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dspike

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Hi all! I have designed fpga (ACEX1k) based device with external SRAM module (single port) and now need to create the internal dual port ram interface with it. I'm looking for any decision. Thanks a lot.
 

you can generate them in quartus 2 fpga developing environment.

best regards


dspike said:
Hi all! I have designed fpga (ACEX1k) based device with external SRAM module (single port) and now need to create the internal dual port ram interface with it. I'm looking for any decision. Thanks a lot.
Click to expand...
 

funster said:
you can generate them in qu(at)rtus 2 fpga developing environment.

best regards
Click to expand...

ok. I try to describe the problem in details. Look at the figure, please.
 

give more info like clock domains n how the controller works....can both writing ports write at the same time....i mean tell sth abt the protocol(rules) u follow for reading and writing...tht'll change the way u can design ur RAM.....
 

Did those tricks lots of times in telecom fpga's

16Mhz + 75 = 91 Mhz, so bandwith will fit a 100 mhz device.

Assuming everything synchronous, and ram has no problems with mixed read/writes (SRAM) then use a mux that switches all address/data/rw lines.
It has to give out of 5 timeslots 4 to the 75 mhz device, and 1 timeslot to the 16 mhz one.

Hope this helps

Arnoud
 

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