How to insert delay on a Bidirectional bus in VHDL?

vhdl bidirectional delay

I need to insert some user defined delay on a bidirectional bus in VHDL. Ho wcan I do this?
I am using a delay inserting module as follows:

library IEEE;
use IEEE.Std_Logic_1164.all;

entity WireDelay is
generic (Delay_g : time);
port
(A : inout Std_Logic;
B : inout Std_Logic
);
end WireDelay;


architecture WireDelay_a of WireDelay is
begin
ABC0_Lbl: process
variable ThenTime_v : time;
begin
wait on A'transaction, B'transaction
until ThenTime_v /= now;
-- Break
wait for Delay_g; -- wire delay
ThenTime_v := now;
A <= 'Z';
B <= 'Z';
wait for 0 ns;

-- Make
A <= B;
B <= A;
end process ABC0_Lbl;
end WireDelay_a;


I am using above module for bidirectional as unidirectional buses also. It doesn't work out. For unidirectional signal suppose connected to port A, it doesn't get transfered properly on port B. Shows some 'Z' on port B at output for a delta delay.
How can I resolve this problem?