Difference between "Pulse Skipping" and "Burs

pulse skipping mode

Can any one tell me the difference between the "pulse skipping" and "the "burst mode" commonly used in dc-dc converter to reduce switching loss.

Thanks
Scottie

pulse skipping mode operation

pulse skipping = stop switching , change the pulse density.every clock cycle is the same frequency as normal working.

burst mode is LTC patented control mode.more like real PFM control. They use Current Limit to stop one pulse .The total switching will less then pulse skipping mode, but will cause vout ripple when you increase the inductor peak to peak current as one pulse area.

pulse skipping vs. burst mode

Thanks. Still, I have some follow up questions.

For the pulse skipping, I want to know how the control loop is operating. Any one has related doc for me? Thanks ^ 1000
Also, I am a bit unclear on how pulse skipping reducing switching loss. As I read some document that pulse skipping occurs when the "supposed duty cycle" is equal or smaller that the minimum one offered by the controller, pulse is skipped to maintain regulation. If then, pulse skipping only occurs at very light load (e.g. 100uA range), the middle load range (e.g. 10mA) efficiency is already too poor for further improvement. So, either I miss understand it or .....

For the burst mode, any related doc? Thanks

Scottie

sendoh2000 said:

pulse skipping = stop switching , change the pulse density.every clock cycle is the same frequency as normal working.

burst mode is LTC patented control mode.more like real PFM control. They use Current Limit to stop one pulse .The total switching will less then pulse skipping mode, but will cause vout ripple when you increase the inductor peak to peak current as one pulse area.

Click to expand...

pulse skip burst

You can easily find these two control mode in some DCDC 's datasheet.
TI's tps62200 , LTC3406.

The pulse skipping is one of the regulator's control mode, it was not "occurs when the "supposed duty cycle" is equal or smaller that the minimum one offered by the controller, pulse is skipped to maintain regulation. If then, pulse skipping only occurs at very light load (e.g. 100uA range)"

There's some dc-dc always work at pulse skip mode.Because it's very easy to design and no stability issue ,no need compensation ...

At normal PWM dcdc ,especially current mode control , they use skip pulse at light load to improve light load efficiency. Normally, Power loss at dcdc contains Mosfet conduction loss, switching loss,Iq loss. When light load ,Iq loss and Switching loss will become dominant.skip pulse mode "skipped some pulse" to reduce switching loss. So , the pulse skipping mode's threshold at PWM dcdc will design by 2 efficiency curve ,one is always pulse skipping one is PWM . To find out a Loading to change the control mode to get the best efficiency curve.

You can find these at datasheet.

ps:I'm IC designer in China. I'm familiar with dcdc(buck,boost,buck-boost,chargepump ,current mode,voltage mode ...) I don't know how to post file in this BBS ,if you want discuss with me or get some related documents, you can mail to sendoh @ live.cn
Or use MSN call me ,still the same user id :sendoh @ live.cn