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Whats the problem with this code///

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appu1985

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Code:
module out2(j,w,y,xi,psw,g,w1);

input [7:0]j;
input [15:0] y;
input [7:0] xi;
input [23:0] w ;
input [23:0]psw;


wire  [15:0]d;
wire  [23:0]out;
wire  [23:0]temp;		
wire  [23:0]temp1;
wire  [15:0]y2;
reg   [7:0]k;						
output [23:0]g;
output [23:0]w1;

integer i;		
initial 
begin
temp1 = 0;
end
assign k = j;
			for ( i =1;i<=k;i=i+1)
			begin temp1 = temp1 + (w[i]*y[i]);
			end
			assign g = psw + temp1;//Evaluated the Partial Sum uptill now
			
			assign w1 = (xi * y[j]) + (y[j]*w[j]) - (y[j]*g);   
			
endmodule
 

Verilog is a hardware description language, not a sequential programming language. You can't do a sum-of-products in a 'for' loop. Your module doesn't even have a clock.

Search for tutorials or examples of digital signal processing in Verilog. Sum-of-products is a common operation in DSP.
 

Do you want this code to synthesize into hardware? If so, as has been pointed out, you will have to do something drastically different as this is not synthesizeable.

If you want this to be behavioural code, then you will need to put the for loop within either an initial or always block. assign statements must be outside an initial or always block.

r.b.
 

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